3.5.43. TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR, ETMv3.4

The ETMTESSEICR characteristics are:

Purpose

Specifies the EmbeddedICE watchpoint comparator inputs that are used as trace start and stop resources.

Usage constraints

There are no usage constraints.

Configurations

This register is only available in ETMv3.4 or later.

The number of EmbeddedICE watchpoint comparators is implementation defined, is specified by ETMCCER bits [19:16], and can be zero. See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later. If the ETM does not implement any EmbeddedICE watchpoint comparators then the ETMTESSEICR is RAZ/WI.

If the ETM implements fewer than eight EmbeddedICE watchpoint comparators, the high order bits of the resource select fields are RAZ/WI.

Attributes

See the register summary in Table 3.3.

Figure 3.40 shows the ETMTESSEICR bit assignments.

Figure 3.40. ETMTESSEICR bit assignments

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Table 3.54 shows the ETMTESSEICR bit assignments.

Table 3.54. ETMTESSEICR bit assignments

Bits

Version [a]

Description

[31:24]-Reserved, Read-as-zero.

[23:16]

v3.4

Stop resource selection. Setting a bit in this field to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable stop resource. Bit [16] corresponds to input 1, bit [17] to input 2, and this pattern continues up to bit [23] corresponding to input 8.

[15:8]-Reserved, Read-as-zero.

[7:0]

v3.4

Start resource selection. Setting a bit in this field to 1 selects the corresponding EmbeddedICE watchpoint input as a TraceEnable start resource. Bit [0] corresponds to input 1, bit [1] to input 2, and this pattern continues up to bit [7] corresponding to input 8.

[a] The first ETM architecture version that defines the field.


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