A.2. Summary of implementation defined ETM features

This section lists the ETM features that are implementation defined, for ETMv3.4. It also indicates how, for a particular ETM, you can check the actual implementation of each feature. See the descriptions of the different features for information about their support in ETM versions before ETMv3.4.

Table A.29 lists the ETM features where it is implementation defined either:

With all of these features except for the Trace port size, the minimum permitted value is 0, indicating that the feature is not supported in the ETM implementation.

Table A.29. ETMv3.4 features with implementation defined number of instances or size

FeaturePermitted valuesValue given by
Address comparators0-8 pairsBits [3:0] of the ETMCCR. [a]
Data value comparators0-8Bits [7:4] of the ETMCCR. [a]
EmbeddedICE watchpoint comparators0-8Bits [19:16] of the ETMCCER. [b]
Context ID comparators0-3Bits [25:24] of the ETMCCR. [a]
Counters0-4Bits [15:13] of the ETMCCR. [a]
Sequencer0, 1Bit [16] of the ETMCCR. [a]
Memory Map decoder inputs0-16Bits [12:8] of the ETMCCR. [a]
External inputs0-4Bits [19:17] of the ETMCCR. [a]
External outputs0-4Bits [22:20] of the ETMCCR. [a]
Extended external input bus width0-255Bits [10:3] of the ETMCCER. [b]
Extended external input selectors0-4Bits [2:0] of the ETMCCER. [b]
Instrumentation resources0-4Bits [15:13] of the ETMCCER. [b]
Trace port sizeSee textETMCR bits [21,6:4]. See ETM port size encoding.
VMID comparator, ETMv3.50, 1Bit [26] of the ETMCCER.[b]

Table A.30 lists the features that are optional in an ETMv3.4 implementation. This means that, in an ETMv3.4 implementation, it is implementation defined whether each of these features is supported.

Table A.30. Optional features in ETMv3.4

Implementation ofCheck for support by
FIFOFULL controlReading bit [23] of the ETMCCR. [a] See also Processor stalling, FIFOFULL.
Trace Start/Stop blockReading bit [26] of the ETMCCR. [a]
Trace all branchesTesting whether you can set bit [8] of the ETMCR to 1. [b]
Cycle-accurate traceWriting 1 to bit [12] of the ETMCR see Checking support for cycle-accurate tracing, ETMv3.3 and later.
Data trace options [c]Writing 1s to bits [20:18,3:1] of the ETMCR. See Checking available data tracing options, ETMv3.3 and later.
Data address comparisonReading bit [12] of the ETMCCER. [d]
EmbeddedICE behavior controlReading bit [21] of the ETMCCER. [d]
EmbeddedICE inputs to Trace Start/Stop blockReading bit [20] of the ETMCCER. [d]
Alternative address compressionReading bit [20] of the ETMIDR. See ID Register, ETMIDR, ETMv2.0 and later.
OS Lock mechanismReading bit [0] of the ETMOSLSR. See OS Lock Status Register, ETMOSLSR, ETMv3.3 and later.
Secure non-invasive debugReading bits [3:2] of the ETMAUTHSTATUS register. See Authentication Status Register, ETMAUTHSTATUS, ETMv3.2 and later.
Context ID tracingTesting whether you can set bits [15:14] of the ETMCR to b11. [b]
VMID tracingReading bit [26] of the ETMCCER.[d]
Timestamp supportReading bit [28] of the ETMCCER.[d]
Reduced function counterReading bit [27] of the ETMCCER.[d]

[c] Data address tracing, data value tracing, CPRT tracing, data-only trace mode.

In addition to the information in Table A.29 and Table A.30:

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