Embedded Trace Macrocell Architecture Specification: A.2. Summary of implementation defined ETM features

A.2. Summary of implementation defined ETM features

This section lists the ETM features that are implementation defined, for ETMv3.4. It also indicates how, for a particular ETM, you can check the actual implementation of each feature. See the descriptions of the different features for information about their support in ETM versions before ETMv3.4.

Table A.29 lists the ETM features where it is implementation defined either:

the number of times the feature is implemented
the size of the feature.

With all of these features except for the Trace port size, the minimum permitted value is 0, indicating that the feature is not supported in the ETM implementation.

Table A.29. ETMv3.4 features with implementation defined number of instances or size

Feature	Permitted values	Value given by
Address comparators	0-8 pairs	Bits [3:0] of the ETMCCR. ^[a]
Data value comparators	0-8	Bits [7:4] of the ETMCCR. ^[a]
EmbeddedICE watchpoint comparators	0-8	Bits [19:16] of the ETMCCER. ^[b]
Context ID comparators	0-3	Bits [25:24] of the ETMCCR. ^[a]
Counters	0-4	Bits [15:13] of the ETMCCR. ^[a]
Sequencer	0, 1	Bit [16] of the ETMCCR. ^[a]
Memory Map decoder inputs	0-16	Bits [12:8] of the ETMCCR. ^[a]
External inputs	0-4	Bits [19:17] of the ETMCCR. ^[a]
External outputs	0-4	Bits [22:20] of the ETMCCR. ^[a]
Extended external input bus width	0-255	Bits [10:3] of the ETMCCER. ^[b]
Extended external input selectors	0-4	Bits [2:0] of the ETMCCER. ^[b]
Instrumentation resources	0-4	Bits [15:13] of the ETMCCER. ^[b]
Trace port size	See text	ETMCR bits [21,6:4]. See ETM port size encoding.
VMID comparator, ETMv3.5	0, 1	Bit [26] of the ETMCCER.^[b]
^[a]See Configuration Code Register, ETMCCR. ^[b]See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later.

Table A.30 lists the features that are optional in an ETMv3.4 implementation. This means that, in an ETMv3.4 implementation, it is implementation defined whether each of these features is supported.

Table A.30. Optional features in ETMv3.4

Implementation of	Check for support by
FIFOFULL control	Reading bit [23] of the ETMCCR. ^[a] See also Processor stalling, FIFOFULL.
Trace Start/Stop block	Reading bit [26] of the ETMCCR. ^[a]
Trace all branches	Testing whether you can set bit [8] of the ETMCR to 1. ^[b]
Cycle-accurate trace	Writing 1 to bit [12] of the ETMCR see Checking support for cycle-accurate tracing, ETMv3.3 and later.
Data trace options ^[c]	Writing 1s to bits [20:18,3:1] of the ETMCR. See Checking available data tracing options, ETMv3.3 and later.
Data address comparison	Reading bit [12] of the ETMCCER. ^[d]
EmbeddedICE behavior control	Reading bit [21] of the ETMCCER. ^[d]
EmbeddedICE inputs to Trace Start/Stop block	Reading bit [20] of the ETMCCER. ^[d]
Alternative address compression	Reading bit [20] of the ETMIDR. See ID Register, ETMIDR, ETMv2.0 and later.
OS Lock mechanism	Reading bit [0] of the ETMOSLSR. See OS Lock Status Register, ETMOSLSR, ETMv3.3 and later.
Secure non-invasive debug	Reading bits [3:2] of the ETMAUTHSTATUS register. See Authentication Status Register, ETMAUTHSTATUS, ETMv3.2 and later.
Context ID tracing	Testing whether you can set bits [15:14] of the ETMCR to b11. ^[b]
VMID tracing	Reading bit [26] of the ETMCCER.^[d]
Timestamp support	Reading bit [28] of the ETMCCER.^[d]
Reduced function counter	Reading bit [27] of the ETMCCER.^[d]
^[a]See Configuration Code Register, ETMCCR. ^[b]See Main Control Register, ETMCR. ^[c]Data address tracing, data value tracing, CPRT tracing, data-only trace mode. ^[d]See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later.

In addition to the information in Table A.29 and Table A.30:

It is implementation defined which combinations of Port size and Port mode are supported. To test whether a particular combination is supported:
- write the required values to bits [21,6:4] (Port size) and bits [13,17:16] of the ETMCR.
- read bits [11:10] of the ETMSCR to see if the selected port mode and port size are supported.
Before ETMv3.3, some of the behavior of the address range comparators is implementation defined when the Exact match bit of the Address Access Type Register is set to 1. For more information see Behavior of address comparators.

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