4.10.4. Exception return instructions

Table 4.4 shows the instructions that generate an exception return when the instruction passes its condition code check.

Table 4.4. Exception return instructions

DescriptionExample MnemonicARM Profile
Load multiple with the PC and CPSR

LDM (exception return)

v-7A, v7-R, ARMv6 and earlier
Return from Exception

RFE

Data processing instruction that modifies the PC and has the S bit set

MOVS PC, LR PC, SUBS PC, LR

Exception return[a]

ERET

POP or LDM that loads into the PC

LDM, POP

v7-M[b]
Load to the PC

LDR PC

Branch and exchange with any register

BX Rn

[a] Only if the Virtualization Extensions are implemented. See Virtualization Extensions, ETMv3.5.

[b] In ARMv7-M, these instructions are only considered to be exception return instructions if they transfer one of the special values into the PC.


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