7.3.8. Exceptions when leaving Debug state

The following sections describe trace when exceptions occur as the processor is leaving Debug state.

Processor reset

If a processor reset occurs while the processor is in Debug state, the processor usually leaves Debug state and restarts execution at the reset vector. It is implementation defined whether the reset exception is indicated. For example, the ETM might trace one of the following sequences:

  • An I-Sync packet with the address of the reset vector and a reason code of Debug Exit, without indicating the reset exception.

  • An I-Sync packet with the address of an instruction before the reset occurred, followed by a branch packet indicating the reset exception and branching to the reset vector.

Other exceptions

If an exception occurs before the processor executes any instructions after leaving Debug state, it is implementation defined whether the exception is traced. For example, if an interrupt exception is taken before any instructions are executed after leaving Debug state, the ETM might trace one of the following sequences:

  • An I-Sync packet with the address indicating the interrupted instruction, followed by a branch packet indicating the interrupt exception. If an instruction is traced between the I-Sync and the branch packet, using a p-header packet, this instruction is canceled by the branch packet.

  • An I-Sync packet with the address of the interrupt vector. The interrupt exception is not explicitly traced.

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