4.10.1. Load/Store Multiple (LSM) instructions

Some sections of this specification refer to Load/Store Multiple (LSM) instructions. These are instructions that passed their condition codes and cause more than one data transfer.

The LSM instructions are:

LDC{2}

Load coprocessor.

LDM{<amode>}

Load multiple.

LDRD

Load register dual.

LDREXD

Load register exclusive doubleword.

MCRR{2}

Move to coprocessor from two ARM core registers.

MRRC{2}

Move to two ARM core registers from coprocessor.

POP

Pop multiple registers.

PUSH

Push multiple registers.

RFE

Return from exception.

SRS

Save return state.

STC{2}

Store coprocessor.

STM{<amode>}

Store multiple.

STRD

Store register dual.

STREXD

Store register exclusive doubleword.

SWP

Swap a word.

SWPB

Swap a byte.

VLDM

Vector load multiple. Loads multiple extension registers from consecutive memory locations.

VLDn

Vector load, where n is the number of elements to load, from 1 to 4.

VLDR.64

Vector load register, 64-bit option.

VMOV, between two ARM core registers and two single-precision registers

Vector move that transfers the contents between two single-precision VFP registers and two ARM core registers.

VMOV, between two ARM core registers and a doubleword extension register

Vector move that transfers the contents between two ARM core registers and a doubleword extension register.

VPOP

Vector pop. Loads multiple consecutive extension registers from the stack.

VPUSH

Vector push. Stores multiple consecutive extension registers to the stack.

VSTM

Vector store multiple. Stores multiple extension registers to consecutive memory locations.

VSTn

Vector store, where n is the number of elements to store, from 1 to 4.

VSTR.64

Vector store register, 64-bit option.

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