3.5.71. Peripheral ID4 Register, ETMPIDR4

The ETMPIDR4 characteristics are:


This register holds peripheral identification information.

Usage constraints

Only bits [7:0] of this register are valid. They must be used with bits [7:0] of the other Peripheral ID registers to obtain the CoreSight Peripheral ID for the ETM macrocell.


This register is only available in ETMv3.2 or later.


See the register summary in Table 3.3 and Reset behavior.

Figure 3.66 shows the ETMPIDR4 bit assignments.

Figure 3.66. ETMPIDR4 bit assignments

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.

Table 3.81 shows the ETMPIDR4 bit assignments.

Table 3.81. ETMPIDR4 bit assignments

BitsDefined in ETM architecture versionsDescription [a]
[7:4]v3.2 and later4KB count
[3:0]v3.2 and laterJEP106 Continuation Code

[a] See Table 3.76 for more information about the register fields.

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q