3.4. The ETM registers

Table 3.3 shows the ETM registers, in register order. In the table, access type is described as follows:


Read and write.


Read only.


Write only.

Table 3.3. ETM register summary

Register [a]





0x000-0x0BF, ETM Trace Registers[c]
0x000Main Controlv1.0RWSee Main Control Register, ETMCR
0x001Configuration Codev1.0ROSee Configuration Code Register, ETMCCR
0x002Trigger Eventv1.0WO[d]See Trigger Event Register, ETMTRIGGER
0x003ASIC Controlv1.0WO[d]See ASIC Control Register, ETMASICCR
0x004Statusv1.1 to v3.0ROSee ETM Status Register, ETMSR, ETMv1.1 and later
0x005System Configurationv1.2ROSee System Configuration Register, ETMSCR, ETMv1.2 and later
TraceEnable configuration
0x006TraceEnable Start/Stop Controlv1.2WO[d]See TraceEnable Start/Stop Control Register, ETMTSSCR, ETMv1.2 and later
0x007TraceEnable Control 2v1.2WO[d]See TraceEnable Control 2 Register, ETMTECR2, ETMv1.2 and later
0x008TraceEnable Eventv1.0WO[d]See TraceEnable Event Register, ETMTEEVR
0x009TraceEnable Control 1v1.0WO[d]See TraceEnable Control 1 Register, ETMTECR1
FIFOFULL configuration
0x00AFIFOFULL Regionv1.0WO[d]See FIFOFULL Region Register, ETMFFRR
0x00BFIFOFULL Levelv1.x onlyWOSee FIFOFULL Level Register, ETMFFLR
ViewData configuration
0x00CViewData Eventv1.0WO[d]See ViewData Event Register, ETMVDEVR
0x00DViewData Control 1v1.0WO[d]See ViewData Control 1 Register, ETMVDCR1
0x00EViewData Control 2v1.0WO[d]See ViewData Control 2 Register, ETMVDCR2

ViewData Control 3

v1.0WO[d]See ViewData Control 3 Register, ETMVDCR3
Address comparators
0x010- 0x01FAddress Comparator Value 1-16v1.0WO[d]See Address Comparator Value Registers, ETMACVRn
0x020- 0x02FAddress Comparator Access Type 1-16v1.0WO[d]See Address Comparator Access Type Registers, ETMACTRn

Data value comparators


Only the even-numbered registers can be implemented. The odd-numbered registers are reserved.

0x030- 0x03E, even

Data Comparator Value 1-16

v1.0WO[d]See Data Comparator Value Registers, ETMDCVRn

0x031- 0x03F, odd

0x040- 0x04E, evenData Comparator Mask 1-16v1.0WO[d]See Data Comparator Mask Registers, ETMDCMRn
0x041- 0x04F, odd---Reserved
0x050- 0x053Counter Reload Value 1-4v1.0WO[d]See Counter Reload Value Registers, ETMCNTRLDVRn
0x054- 0x057Counter Enable 1-4v1.0WO[d]See Counter Enable Registers, ETMCNTENRn
0x058- 0x05BCounter Reload Event 1-4v1.0WO[d]See Counter Reload Event Registers, ETMCNTRLDEVRn
0x05C- 0x05FCounter Value 1-4v1.0 to v3.0ROSee Counter Value Registers, ETMCNTVRn
0x060- 0x065Sequencer State Transition Eventv1.0WO[d]See Sequencer State Transition Event Registers, ETMSQabEVR
0x067Current Sequencer Statev1.0 to v3.0ROSee Current Sequencer State Register, ETMSQR
0x068- 0x06BExternal Output Event 1-4v1.0WO[d]See External Output Event Registers, ETMEXTOUTEVRn
Context ID comparators
0x06C- 0x06EContext ID Comparator Valuev2.0WO[d]See Context ID Comparator Value Registers, ETMCIDCVRn
0x06FContext ID Comparator Maskv2.0WO[d]See Context ID Comparator Mask Register, ETMCIDCMR
Other ETM Trace[c] registers
0x070- 0x077Implementation- specific WO [d]See Implementation specific registers
0x078Synchronization Frequencyv2.0WO[d] or RO[e]See Synchronization Frequency Register, ETMSYNCFR, ETMv2.0 and later
0x079IDv2.0ROSee ID Register, ETMIDR, ETMv2.0 and later
0x07AConfiguration Code Extensionv3.1ROSee Configuration Code Extension Register, ETMCCER, ETMv3.1 and later
0x07BExtended External Input Selectionv3.1WO[d]See Extended External Input Selection Register, ETMEXTINSELR, ETMv3.1 and later
0x07CTraceEnable Start/Stop EmbeddedICE Controlv3.4WO[d]See TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR, ETMv3.4
0x07DEmbeddedICE Behavior Controlv3.4WO[d]See EmbeddedICE Behavior Control Register, ETMEIBCR, ETMv3.4 and later
0x07ETimestamp Event Registerv3.5RWSee Timestamp Event Register, ETMTSEVR, ETMv3.5
0x07FAuxiliary Control Registerv3.5RWSee Auxiliary Control Register, ETMAUXCR, ETMv3.5
0x080CoreSight Trace IDv3.2RWSee CoreSight Trace ID Register, ETMTRACEIDR, ETMv3.2 and later
0x082ETM ID Register 2v3.5ROSee ETM ID Register 2, ETMIDR2, ETMv3.5
0x090VMID Comparator Value Registerv3.5RWSee VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5
0x0C0-0x0C5, ETM Management Registers[c]
 Operating system save and restore registers
0x0C0OS Lock Accessv3.3WOSee OS Lock Access Register, ETMOSLAR, ETMv3.3 and later
0x0C1OS Lock Statusv3.3ROSee OS Lock Status Register, ETMOSLSR, ETMv3.3 and later
0x0C2OS Save and Restorev3.3RWSee OS Save and Restore Register, ETMOSSRR, ETMv3.3 and later
 Other ETM Management registers
0x0C4Power Down Control Registerv3.5RWPower Down Control Register, ETMPDCR, ETMv3.5
0x0C5Device Power-Down Statusv3.3RWSee Device Power-Down Status Register, ETMPDSR, ETMv3.3 and later
0x0C6-0x3BF, ETM Trace Registers[c]
0x380-0x3BFIntegration registersv3.2-Reserved for implementation defined topology detection and integration registers
0x3C0-0x3FF, ETM Management Registers[c]
0x3C0Integration Mode Controlv3.2RWSee Integration Mode Control Register, ETMITCTRL, ETMv3.2 and later
0x3E8Claim Tag Setv3.2RWSee Claim Tag Set Register, ETMCLAIMSET
0x3E9Claim Tag Clearv3.2RWSee Claim Tag Clear Register, ETMCLAIMCLR
0x3ECLock Accessv3.2WO[d]See Lock Access Register, ETMLAR, ETMv3.2 and later
0x3EDLock Statusv3.2ROSee Lock Status Register, ETMLSR, ETMv3.2 and later
0x3EEAuthentication Statusv3.2ROSee Authentication Status Register, ETMAUTHSTATUS, ETMv3.2 and later
0x3F2Device Configurationv3.2ROSee CoreSight Device Configuration Register, ETMDEVID, ETMv3.2 and later
0x3F3Device Typev3.2ROSee CoreSight Device Type Register, ETMDEVTYPE, ETMv3.2 and later
Peripheral and Component ID registers
0x3F4Peripheral ID4v3.2ROSee Peripheral ID4 Register, ETMPIDR4
0x3F5Peripheral ID5v3.2ROSee Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR7
0x3F6Peripheral ID6v3.2RO
0x3F7Peripheral ID7v3.2RO
0x3F8Peripheral ID0v3.2ROSee Peripheral ID0 Register, ETMPIDR0
0x3F9Peripheral ID1v3.2ROSee Peripheral ID1 Register, ETMPIDR1
0x3FAPeripheral ID2v3.2ROSee Peripheral ID2 Register, ETMPIDR2
0x3FBPeripheral ID3v3.2ROSee Peripheral ID3 Register, ETMPIDR3
0x3FCComponent ID0v3.2ROSee Component ID0 Register, ETMCIDR0
0x3FDComponent ID1v3.2ROSee Component ID1 Register, ETMCIDR1
0x3FEComponent ID2v3.2ROSee Component ID2 Register, ETMCIDR2
0x3FFComponent ID3v3.2ROSee Component ID3 Register, ETMCIDR3

[a] The Register column gives the register number. Registers are numbered sequentially from zero. Where registers are accessed in a memory-mapped scheme, the offset of a register is (4 x register number).

[b] The first ETM architecture to define the register, or (if the register type is different in different architecture versions) the first architecture version to which the description applies.

[c] The split into Trace and Management registers applies from ETMv3.3. See ETM Trace and ETM Management registers, from ETMv3.3.

[d] In ETMv3.1 and later, register is read/write if bit [11] of the ETMCCER is set to 1. See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later.

[e] From ETMv3.4, it is implementation defined whether the Synchronization Frequency register is implemented as a write-only register that is read/write when bit [11] of the ETMCCER, register 0x7A, is set to 1, or as a read-only register. See the register description for more information.

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q