3.3.2. Topology detection requirements

All ETMs implement the logical interfaces shown in Table 3.2. These logical interfaces must implement registers to support topology detection, as described in the CoreSight Architecture Specification.

Table 3.2. ETM logical interfaces

Trace output Master 1
Processor interface Slave 1 + (value of bits [14:12] of ETMSCR, register 0x005)
External output Master Value of bits [22:20] of ETMCCR, register 0x001
External inputSlave Value of bits [19:17] of ETMCCR, register 0x001
Trigger output Master1

Registers 0x380-0x3BF are reserved for topology detection and integration registers, and use of these registers for this purpose is implementation defined.

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