3.5.6. System Configuration Register, ETMSCR, ETMv1.2 and later

The ETMSCR characteristics are:

Purpose

Shows the ETM features supported by the ETM macrocell. The contents of this register are based on inputs provided by the ASIC.

Usage constraints

There are no usage constraints.

Configurations

Only implemented in ETMv1.2 and later.

Attributes

See the register summary in Table 3.3, and Reset behavior.

Figure 3.10 shows the ETMSCR bit assignments, for ETM architecture version 3.2. See Table 3.16 for the differences in other architecture versions.

Figure 3.10. ETMSCR bit assignments for architecture v3.2

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Table 3.16 shows the ETMSCR bit assignments, and describes the differences between different ETM architecture versions.

Table 3.16. ETMSCR bit assignments

Bits

Version [a]

Description

[31:18]-Reserved.
[17]v2.1No Fetch comparisons. If this bit is set to 1, address comparators cannot perform fetch-stage comparisons. Setting bits [2:0] of an ETMACTR to b000, instruction fetch causes the comparator to have unpredictable behavior.
[16:15]-Reserved.
[14:12]v3.2

Number of supported processors minus 1.

The value given here is the maximum value that can be written to bits [27:25] of the ETMCR, register 0x000. This field must be b000 if the ETM supports Direct JTAG access.

[11]v3.0

Port mode supported.

Set to 1 if the currently selected port mode is supported internally or externally.

[10]v3.0

Port size supported.

Set to 1 if the currently selected port size is supported internally or externally for the currently selected port mode. Enables more complex port sizes to be supported.

[9]v3.0Maximum port size[3]. This bit is used in conjunction with bits [2:0].

[8]

v1.3

If set to 1, FIFOFULL is supported. This bit is used in conjunction with bit [23] of the ETMCCR, register 0x001.

Note

You can use FIFOFULL only if it is supported by both your ETM and your system. Some processors do not support FIFOFULL, so it cannot be used by the system.

[7]

v2.x and earlier

If set to 1, demultiplexed trace data format is supported.

v3.0 and laterReserved, reads as zero. Use bit [11] instead.
[6]v2.x and earlier

If set to 1, multiplexed trace data format is supported.

v3.0 and laterReserved, reads as zero. Use bit [11] instead.

[5]

v2.x and earlier

If set to 1, normal trace data format is supported.

v3.0 and laterReserved, reads as zero. Use bit [11] instead.

[4]

v2.x and earlier

If set to 1, full-rate clocking is supported.

v3.0 and laterReserved, reads as zero. Full-rate clocking is no longer supported.

[3]

v2.x and earlier

If set to 1, half-rate clocking is supported.

v3.0 and laterReserved, Read-As-One. All modes use half-rate clocking.

[2:0]

v1.2 and later

Maximum port size[2:0]. This bit is used in conjunction with bit [9]. The value given here is the maximum size supported by both the ETM and the ASIC. Smaller sizes might or might not be supported. Check bit [10] for precise information on supported modes. See bits [6:4] in Table 3.5.

[a] The first ETM architecture version that defines the field, or (where the use of a field is different in different versions) the first architecture version to which the description applies.


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