5.1. ETMv1 pipeline status signals

You can consider the pipeline status as a view of the Execute stage of the pipeline. Any side effects of the instruction, for example an aborted load or a write to the PC, are observed immediately, before the pipeline status for the next instruction is generated. This means that the protocol is independent of the exact pipeline implementation of the ARM processor.

Each executed instruction generates a single pipeline status message on the PIPESTAT pins of the port. These are shown in Table 5.1.

Table 5.1. PIPESTAT messages







Instruction Executed

Indicates an instruction has been executed that has not generated any associated trace packets. This includes load or store instructions that did not have their data traced. Usually used for an operation that did not cause a branch, but it is also used for direct branches, that is where the destination can be worked out by referring back to the code image.



Instruction Executed with Data

A load or store instruction has been executed, and the memory access is output on the trace port.



Instruction Not Executed

An instruction has reached the Execute stage of the pipeline, but failed its condition code test.




No instruction was executed in the cycle and the pipeline has not advanced. This might be for several reasons. For example, the memory system might have asserted the wait signal to the processor, or the processor might be performing an internal cycle. Wait cycles are also generated when tracing is disabled.

Wait cycles are used to output trace packet data. If no packet is output in this cycle, this status is replaced by Trace Disabled.



Branch Executed

This is generated when an indirect branch is executed (that is a branch whose target address cannot be directly inferred from the source code). A destination address is required for the branch.

Direct branches can also generate this status. The trace port can optionally be switched into a mode where it outputs this status for all branches.



Branch Executed with Data

Used whenever a data access causes a branch, (occurs when a load instruction has the PC as the destination register).




Indicates that a trigger condition has occurred. See Trigger PIPESTAT signals.



Trace Disabled

The trace might be disabled to prevent the TPA from filling up with unwanted information. This encoding is used when the trace is disabled or when no packet is output on a wait cycle.

For multi-cycle instructions, and for cycles where the memory system has asserted a wait signal, wait cycles are indicated.

Instructions that are fetched but not executed, because of an executed branch, are not indicated as Instruction Not Executed (IN), but as Wait (WT). Only instructions that reach the Execute stage of the pipeline are traced, with the exception of instructions that are canceled because of an interrupt, prefetch abort, or processor Reset exception (see Exceptions).

Every time the processor performs a branch operation (BE or BD), at least two instructions that have been fetched into the pipeline are discarded. However, for the two cycles after a branch, the pipeline status pins are re-used to output an address packet offset that indicates how many branch addresses are currently in the on-chip FIFO. For more information, see Address Packet Offset.

The association between trace packets and pipeline status signals is summarized in Pipeline status and trace packet association in ETMv1.

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q