A.1.2. Resource control registers

This section contains register tables for ETM resource control. These are Table A.4 to Table A.28.

Table A.4. ETMASICCR, register 0x003

Bits

Description

[7:0]

ASIC control


Table A.5. ETMTSSCR, register 0x006

Bits

Description

[31:16]

When a bit is set to 1, it selects a single address comparator 16 to 1 as stop addresses. For example, bit [16] set to 1 selects single address comparator 1.

[15:0]

When a bit is set to 1, it selects a single address comparator 16 to 1 as start addresses. For example, bit [0] set to 1 selects single address comparator 1.


Table A.6. ETMTECR1, register 0x009

Bits

Description

[25]

Trace start/stop enable:

0

Tracing is unaffected by the trace start/stop logic (ETMv1.2 and later).

1

Tracing is controlled by trace on and off addresses.

[24]

Include/exclude control:

0

Include. The specified resources indicate the regions in which tracing can occur. When outside this region tracing is prevented.

1

Exclude. The resources specified in bits [23:0] and in the ETMTECR2 indicate regions to be excluded from the trace. When outside an exclude region, tracing can occur.

[23:8]

When a bit is set to 1, it selects a memory map decode 16 to 1 for include/exclude control. For example, bit [8] set to 1 selects MMD 1.

[7:0]

When a bit is set to 1, it selects an address range comparator 8 -1 for include/exclude control. For example, bit [0] set to 1 selects address range comparator 1.


Table A.7. ETMTECR2, register 0x007

Bits

Description

[15:0]

When a bit is set to 1, it selects single address comparator 16 to 1 for include/exclude control. For example, bit [0] set to 1 selects single address comparator 1.


Table A.8. ETMFFRR, register 0x00A

Bits

Description

[24]

Include/exclude control:

0

Include. The specified resources indicate the regions in which FIFOFULL can be asserted. When outside these regions, FIFOFULL cannot be asserted.

1

Exclude. The resources specified in bits [23:0] indicate the regions in which FIFOFULL cannot be asserted. When outside these regions FIFOFULL can be asserted.

[23:8]

When a bit is set to 1, it selects memory map decode 16 to 1 for include/exclude control. For example, bit [8] set to 1 selects MMD 1.

[7:0]

When a bit is set to 1, it selects address range comparator 8-1 for include/exclude control. For example, bit [0] set to 1 selects address range comparator 1.


Table A.9. ETMFFLR, register 0x00B

Bits

Access

Description

[7:0]

Write-only (ETMv1.x)

Read-only (ETMv2.x)

The number of bytes left in the FIFO, below which the FIFOFULL signal is asserted


Table A.10. ETMVDCR1, register 0x00D

Bits

Description

[31:16]

When a bit is set to 1, it selects single address comparator 16 to 1 for exclude control. For example, bit [16] set to 1 selects single address comparator 1.

[15:0]

When a bit is set to 1, it selects single address comparator 16 to 1 for include control. For example, bit [0] set to 1 selects single address comparator 1.


Table A.11. ETMVDCR2, register 0x00E

Bits

Description

[31:16]

When a bit is set to 1, it selects memory map decode 16 to 1 for exclude control. For example, bit [16] set to 1 selects MMD 1.

[15:0]

When a bit is set to 1, it selects memory map decode 16 to 1 for include control. For example, bit [0] set to 1 selects MMD 1.


Table A.12. ETMVDCR3, register 0x00F

Bits

Description

[16]

Exclude-only control:

0

Mixed mode. ViewData operates in a mixed mode, and both include and exclude resources can be programmed.

1

Exclude-only mode. ViewData is programmed only in an excluding mode. If none of the excluding resources match, tracing can occur.

[15:8]

When a bit is set to 1, it selects address range comparator 8 -1 for exclude control. For example, bit [8] set to 1 selects address range comparator 1.

[7:0]

When a bit is set to 1, it selects address range comparator 8-1 for include control. For example, bit [0] set to 1 selects address range comparator 1.


Table A.13. ETMACVRs, registers 0x010-0x01F

Bits

Description

[31:0]

Address value


Table A.14. ETMACTRs, registers 0x020-0x02F

Bits

Description

[15]

(ETMv3.5)

VMID comparison enable:

0

Ignore VMID.

1

Match only if VMID matches value of ETMVMIDCVR.

This bit is reserved, RAZ if the processor does not implement the Virtualization extensions.

[14]

(ETMv3.5)

Hyp mode comparison enable:

0

Ignore Hyp mode.

1

Consider Hyp mode operation for comparator matching.

This bit is reserved, RAZ if the processor does not implement the Virtualization extensions.

[13:10]

(ETMv3.5)

State and mode comparison control:

Bit [13, 11]

Non-secure comparison control.

Bit [12, 10]

Secure comparison control.

For each pair of bits, the encoding is:

b00

Match in User and privileged modes in this state.

b01

Do not match in any modes in this state.

b10

Match only in privileged modes in this state.

b11

Match only in User mode in this state.

These bits are reserved, RAZ/WI if the processor does not implement the Security Extensions,.

[11:10]

(ETMv3.2)

Secure mode control:

b00

Security level ignored.

b01

Match only if in Non-secure state.

b10

Match only if in Secure state.

b11

Reserved.

[9:8]

(ETMv2.0 to ETMv3.4)

Context ID comparator control:

b00

Ignore Context ID comparators.

b01

Address comparator matches only if Context ID comparator value 1 matches.

b10

Address comparator matches only if Context ID comparator value 2 matches.

b11

Address comparator matches only if Context ID comparator value 3 matches.

[7]

(ETMv2.0 and later)

Exact match bit. Specifies comparator behavior when exceptions occur. See Table A.15 and Table A.16.

[6:5]

Data value comparison control:

b00

No data value comparison.

b01

Address matches only if data value matches.

b10

Reserved.

b11

Address matches only if data value does not match (ETMv1.2 and later).

[4:3]

Size:

b00

Jazelle instruction or byte data.

b01

Thumb instruction or halfword data.

b10

Reserved.

b11

ARM instruction or word data.

See Comparator access size.

[2:0]

Access type:

b000

Instruction fetch.

b001

Instruction execute.

b010

Instruction executed and passed condition code test (ETMv1.2 and later).

b011

Instruction executed and failed condition code test (ETMv1.2 and later).

b100

Data load or store.

b101

Data load.

b110

Data store.

b111

Reserved.


Table A.15. Exact match bit settings for instruction accesses

Exact match bitInstruction canceledInstruction not canceled
0Comparator matchesComparator matches
1Comparator does not matchComparator matches

Table A.16. Exact match bit settings for data accesses

Data comparator present?

Exact match bit

Cache hit

Cache miss

Data abort

Yes

0

Comparator matches if data value matches

Comparator matchesComparator matches
Yes1

Comparator matches if data value matches

Comparator waitsComparator does not match
No

0

Comparator matchesComparator matchesComparator matches
No1Comparator matches

Comparator matches (ETMv3.0 and earlier)

Comparator does not match

Comparator waits (ETMv3.1 and later)


Table A.17. ETMDCVRs, registers 0x030-0x03F

Bits

Description

[31:0]

Data value


Table A.18. ETMDCMRs, registers 0x040-0x04F

Bits

Description

[31:0]

Data mask


Table A.19. ETMCNTRLDVRs, registers 0x050-0x053

Bits

Description

[15:0]

Counter reload value


Table A.20. ETMCNTENRs, registers 0x054-0x057

Bits

Description

[17]

Count enable source in ETMv1.0. When 0, the counter is continuously enabled and decrements every cycle. When 1, the count enable event is used to enable the counter. ARM recommends that bit [17] is always set to b1and that the count enable event is used to control counter operation.

In ETMv2.0 and later, this bit has no effect and is always one.

[16:0]

Count enable event.


Table A.21. ETMCNTVRs, registers 0x05C-0x05F

Bits

Description

[15:0]

Current counter value


Table A.22. ETMSQR, register 0x067

Bits

Description

[1:0]

Possible values are:

b00

State 1.

b01

State 2.

b10

State 3.


Table A.23. ETMEXTOUTEVRs, registers 0x068-0x06B

Bits

Description

[16:0]

External output event


Table A.24. Locations of the ETMCIDCVRs

Register

Register numberOffset
ETMCIDCVR10x06C0x1B0
ETMCIDCVR20x06D0x1B4
ETMCIDCVR30x06E0x1B8

Table A.25. ETMCIDCVRs, registers 0x06C-0x06E

Bits

Description

[31:0]

Context ID value


Table A.26. ETMCIDCMR, register 0x06F

Bits

Description

[31:0]

Context ID mask value


Table A.27. ETMSYNCFR, register 0x078

Bits

Description

[11:0]

Cycle count value. Default value is 1024.


Table A.28. ETMEXTINSELR, register 0x07B

Bits

Description
[31:24]Fourth extended external input selector
[23:16]Third extended external input selector
[15:8]Second extended external input selector
[7:0]First extended external input selector

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