6.10. FIFO overflow

Sometimes, so much trace information is generated on-chip that the FIFO can overflow. When this occurs the ETM uses a two-stage process to empty the FIFO and restart the trace:

  1. The pipeline status is changed to Wait and the FIFO empties. This ensures that all trace information up to the overflow condition is collected. This trace information might be required to determine the cause of the FIFO overflow.

  2. When the FIFO has drained, if TraceEnable is still active tracing is re-enabled as soon as possible.


Either all or none of the data to be placed in the FIFO in a given cycle must be traced. The ETM must not place any data in the FIFO unless there is room for all the data generated in that cycle.

Bit [0] of the ETMSR is a pending overflow flag, indicating that an overflow has occurred but that the FIFO overflow reason code has not been generated. For more information see ETM Status Register, ETMSR, ETMv1.1 and later. This is required where tracing stops because of an ARM breakpoint, but before tracing can be restarted.

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