6.1.7. Trigger PIPESTAT signals

Rather than having a dedicated pin to indicate a trigger event, a special pipeline status encoding is used.

When a trigger event occurs, the TR pipeline status replaces the current pipeline status and the pipeline status that is replaced is output on the TRACEPKT[3:0] pins. The FIFO draining is stopped for that cycle to enable this to happen, and the decompressor must take account of this.

To ensure that trace trigger events can be used to trigger external logic, such as a logic analyzer, it is important that generation of the TR pipeline status is not delayed. The TR pipeline status must be generated as soon as possible after the trigger event goes active. This means it is possible for a TR to occur before the instruction that caused it is traced.

If a trigger occurs when the FIFO is empty, the replaced PIPESTAT value that appears on TRACEPKT[3:0] is WT (Wait).

If a trigger and a TFO are pending at the same time, the replaced PIPESTAT value that appears on TRACEPKT[3:0] is TD. This is uniquely identifiable as a true TFO because a WT is never converted to a TD (Trace Disabled) when a trigger occurs.

Triggers are never delayed and are guaranteed to be output immediately when generated. If a trigger is pending in the second cycle of a TFO output (or the gap cycle) from a 4-bit port, the trigger occurs and the FIFO output is delayed by an extra cycle to output the remaining TFO nibble(s). See Trigger considerations for more information.

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