6.5.6. Data address synchronization

The full data address output is made every n cycles, where n is the counter value programmed in the ETMSYNCFR, see Synchronization Frequency Register, ETMSYNCFR, ETMv2.0 and later. The default counter value is 1024. Every time the counter reaches zero, the next data address output is always a full 5-byte address.

It is expected that a single counter is used for both data address synchronization and TFOs, and that the counter values are staggered to reduce the likelihood of overflow.

The full address encoding is shown in Figure 6.3.

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q