A Cycle count packet consists of a Cycle count header followed by 1-5 bytes of data, as Figure 7.1 shows. A 1 in bit [7] of each byte indicates that another byte follows, in the same way as branch addresses. Up to 32 bits are output in this way. Any missing high-order bits are 0. This value is a number of Ws, inserted before the most recent Non-periodic I-sync packet. This enables the number of cycles between trace regions to be output efficiently. Future versions of the architecture might support larger cycle counts. For more information see:

A cycle count of zero indicates a counter overflow. When this is encountered, the length of the gap is unknown.

The cycle counter is reset whenever the Programming bit or the power-down bit is set to 1 in the ETMCR, register 0x000. The reset value of the counter is zero, indicating counter overflow.

In ETMv3.0, the cycle count output following overflow or entry to debug state must be ignored. From ETMv3.1, the trace is cycle-accurate through debug state. From ETMv3.1 to ETMv3.4, the trace is cycle-accurate through overflow. In ETMv3.5, the trace is not cycle-accurate through overflow.

When tracing in cycle-accurate mode, a cycle count is required for every Non-periodic I-sync packet to indicate the number of cycles (W atoms) since the last P-header packet prior to the I-sync packet. This is output as follows:

For more information about synchronization, see I-sync instruction synchronization.