4.10.2. Data Instructions

An instruction is a data instruction if it passed its condition code test and caused a data transfer.

Data instructions comprise all LSM instructions and the following:

BXJ

Branch and exchange Jazelle.

CLREX

Clear exclusive.

LDR{T}

Load register.

LDRB{T}

Load register byte.

LDREX

Load register exclusive.

LDREXB

Load register exclusive byte.

LDREXH

Load register exclusive halfword.

LDRH{T}

Load register halfword.

LDRSB{T}

Load register signed byte.

LDRSH{T}

Load register signed halfword.

MCR{2}

Move to coprocessor from ARM core register.

MRC{2}

Move to ARM core register from coprocessor.

STR{T}

Store register.

STRB{T}

Store register byte.

STREX

Store register exclusive.

STREXB

Store register exclusive byte.

STREXH

Store register exclusive halfword.

STRH{T}

Store register halfword.

TB{B|H}

Table branch, Thumb and ThumbEE instruction sets only.

VDUP, ARM core register

Vector duplicate. Duplicates an element from an ARM core register into every element of the destination vector.

VLDR.32

Vector load register, 32-bit option.

VMOV, ARM core register to scalar

Vector move that copies a byte, halfword, or word from an ARM core register into an Advanced SIMD scalar.

VMOV, between ARM core register and single-precision register

Vector move that transfers the contents between a single-precision VFP register and an ARM core register.

VMOV, scalar to ARM core register

Vector move that copies a byte, halfword, or word from an Advanced SIMD scalar to an ARM core register.

VMRS

Vector move, extension system register (FPSCR) to general-purpose register.

VMSR

Vector move, general-purpose register to extension system register (FPSCR).

VSTR.32

Vector store register, 32-bit option.

BXJ might not trace data in all implementations, but can always be treated as a data instruction. It is implementation defined whether data is traced. If data is traced, it is a load of Jazelle local variable 0.

Preload (PLD) instructions are not data instructions because they do not cause any data trace. See Preloads.

Data instructions in Jazelle state are implementation defined.

Note

  • The following instructions are not LSM instructions and are not data instructions even though their mnemonics are the same as other LSM and data instructions:

        VMOV, register

        VMOV, immediate.

  • The following instruction is not a data instruction even though it has the same mnemonic as a data instruction:

        VDUP, scalar.

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