8.4. Timing specifications

There are no inherent restrictions on operating frequency, other than ASIC pad technology and TPA limitations. ASIC designers must provide a TRACECLK as symmetrical as possible, and with set up and hold times as large as possible. TPA designers must conversely be able to support a TRACECLK as asymmetrical as possible, and require set up and hold times as short as possible. The following timing specifications are given as a guide for a TPA that supports TRACECLK frequencies up to around 100MHz.

Note

Actual processor clock frequencies vary according to application requirements and the silicon process technologies used. The maximum operating clock frequencies attained by ARM devices increases over time as a result.

If you adhere to the timing described here, you can use any ARM-approved TPA. Figure 8.3 depicts the timing for TRACECLK.

Figure 8.3. TRACECLK specification

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Table 8.10 shows details of the timing requirements for TRACECLK parameters.

Table 8.10. TRACECLK timing requirements

Parameter

Minimum

Description

Tcyc

Frequency dependent

Clock period

Twl

2ns

LOW pulse width

Twh

2ns

HIGH pulse width


Table 8.11 shows rise and fall time requirements for all ETM clock and data signals.

Table 8.11. Rise and fall time requirements

Parameter

Maximum

Description

Tr3nsClock and data rise time
Tf3nsClock and data fall time

Figure 8.4 shows the setup and hold requirements of the trace data pins with respect to TRACECLK.

Figure 8.4. Trace data specification

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Table 8.12 shows the timing requirements for Figure 8.4.

Table 8.12. Trace port setup and hold requirements

Parameter

Minimum

Description

Ts

3ns

Data setup

Th

2ns

Data hold


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