3.5.23. About the data value comparator registers

Two registers are defined for each data value comparator. The following sections describe these registers:

An ETM can implement up to eight data value comparators.

Operation of data value comparators describes the use of the data value comparator registers.

Note

From ETMv3.3, whether an ETM macrocell supports data address comparisons is implementation defined. If data address comparisons are not implemented then the data value comparator registers are not implemented and Read-As-Zero. See No data address comparator option, ETMv3.3 and later for more information.

The ETM architecture defines the data value comparator registers as even-numbered registers, as Table 3.32 shows. This means that, in a memory-mapped implementation, these registers are doubleword aligned.

Table 3.32. Summary of the data value comparator registers

Data value comparatorETMDCVRETMDCMR
Register number [a]Offset [b]Register number [c]Offset [b]
10x0300x0C00x0400x100
20x0320x0C80x0420x108
30x0340x0D00x0440x110
40x0360x0D80x0460x118
50x0380x0E00x0480x120
60x03A0x0E80x04A0x128
70x03C0x0F00x04C0x130
80x03E0x0F80x04E0x138

[a] Registers 0x031, 0x033, 0x035, 0x037. 0x039, 0x03B, 0x03D, and 0x03F are reserved.

[b] When accessed in a memory-mapped scheme, the register offset is always (4 x (Register number)).

[c] Registers 0x041, 0x043, 0x045, 0x047. 0x049, 0x04B, 0x04D, and 0x04F are reserved.


Note

You can use the data value comparator only to observe data. This means that you can only use the data value comparator with load/store accesses. If the data value comparator is enabled and you configure the address comparator to match against instruction addresses, the behavior is unpredictable.

Alignment considerations

See Operation of data value comparators for information about alignment considerations when programming the ETMDCVRs and ETMDCMRs. These considerations are different for different ETM versions, see Summary of alignment and endianness considerations for different ETM versions.

Associating data value comparators with address comparators

Each data value comparator is permanently associated with a particular address comparator. Data value comparators are assigned sequentially to odd-numbered address comparators. An implementation cannot have more data value comparators than address comparator pairs.

An ETMDCVR and the corresponding ETMDCMR addresses correspond directly to the equivalent ETMACVR. For example, in a system that uses four pairs of address comparators and two data value comparators (a medium-sized configuration), Table 3.33 shows the address mapping.

Table 3.33. Example comparator register associations for a medium-sized configuration

Address comparator

Data value comparator

Number

ETMACVR [a]

Present?

ETMDCVR [a]

ETMDCMR [a]

8

0x017

No

-

-

7

0x016

No

-

-

6

0x015

No

-

-

5

0x014

No

-

-

4

0x013

No

-

-

3

0x012

Yes

0x032

0x042

2

0x011

No

-

-

1

0x010

Yes

0x030

0x040

[a] Register numbers are listed. In a memory-mapped scheme, the register offset is always 4 x (Register number).


Note

Early versions of this specification permitted more data value comparators than address comparator pairs. In such an implementation, the extra data value comparators can be allocated to even-numbered address comparators when all odd-numbered address comparators had a data value comparator allocated, up to a maximum of eight. However, this was never implemented in any of the supported standard configurations and is no longer permitted.

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