3.5.1. Main Control Register, ETMCR

The ETMCR characteristics are:

Purpose

Controls general operation of the ETM, such as whether tracing is enabled or coprocessor data is traced.

Usage Constraints

There are no usage constraints.

Configurations

This register is available in all ETM implementations.

Attributes

See the register summary in Table 3.3, and Reset behavior.

Figure 3.4 shows the ETMCR bit assignments.

Figure 3.4. ETMCR bit assignments

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Table 3.5 shows the ETMCR bit assignments.

Table 3.5. ETMCR bit assignments

Bits

Function

Version [a]

Description

[31]

Reserved

-

Must be written as 0.

[30]

VMID trace enable

v3.5

Set this bit to 1 to enable VMID tracing. See Virtualization Extensions, ETMv3.5.

If bit [26] of the Configuration Code Extension Register is zero, this indicates that the Virtualization Extensions are not implemented, and this bit is RAZ/WI.

An ETM reset sets this bit to 0.

[29]

Reserved

-

Must be written as 0.

[28]

Timestamp enable

v3.5

Set this bit to 1 to enable timestamping. See Timestamping, ETMv3.5.

If bit [22] of the Configuration Code Extension Register is zero, this indicates that timestamping is not implemented, and this bit is RAZ/WI.

An ETM reset sets this bit to 0.

[27:25]

Processor selectv3.2

If an ETM is shared between multiple processors, selects the processor to trace. For the maximum value permitted, see bits [14:12] of the Table 3.16.

To guarantee that the ETM is correctly synchronized to the new processor, you must update these bits as follows:

  1. Set bit [10], ETM programming, to 1.

  2. Poll bit [1] of the ETM Status Register until it is set to 1, see Use of the Programming bit.

  3. Set bit [0], ETM power down, to 1.

  4. Change the Processor select bits.

  5. Clear bit [0], ETM power down, to 0.

  6. Perform other programming required as normal.

The ETM cannot be shared if Direct JTAG access is supported.

On an ETM reset these bits are all zero.

[24]Instrumentation resources access controlv3.3

When this bit is set to 1, the Instrumentation resources can only be controlled when the processor is in a privileged mode.

When this bit is set to 0, the Instrumentation resources can be accessed in both privileged and User modes.

On an ETM reset this bit is 0.

If no Instrumentation resources are implemented this bit reads as zero and ignores writes.

This bit is only writable if at least one instrumentation resource is implemented. Otherwise, it reads as zero and ignores writes.

[23]

Disable software writes

v3.2

Register writes from software disabled.

This bit can only be written by the debugger.

This bit is not supported in all implementations. This bit reads back as zero if not supported.

On an ETM reset this bit is 0.

[22]Disable register writes from the debuggerv3.1

Register writes from the debugger disabled. This bit can only be written by software.

Note

Typically a debugger can halt the processor to simulate software accesses. This means that, even if this bit is set, the debugger might be able to access the ETM registers.

This bit is not supported in all implementations. This bit reads as zero if not supported.

On an ETM reset this bit is 0.

[21]Port size[3]v3.0

For ETMv3.0 and later use this in conjunction with bits [6:4].

On an ETM reset this bit is 0.

[20]Data-only modev3.1

The possible values of this bit are:

0

Instruction trace enabled.

1

Instruction trace disabled. Data-only tracing is possible in this mode.

On an ETM reset this bit is 0.

[19]

Filter (CPRT)

v3.0

In ETMv2.x and earlier, CPRT tracing ignores ViewData and is controlled by a single bit, bit [1] of this register. From ETMv3.0, this bit is used in conjunction with bit [1], the MonitorCPRT bit. See Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later.

On an ETM reset this bit is 0.

[18]

Suppress data

v3.0

Used with bit [7] to suppress data. See Data suppression.

On an ETM reset this bit is 0.

For information about the interaction of this bit with bit [7] see Processor stalling, FIFOFULL.

[17:16]

Port mode

v1.2    up to v2.1  

These bits enable the trace port clocking mode to be set. See Trace port clocking modes.

On a TAP reset or ETM reset these bits are cleared to 0.

Port mode [1:0]

v3.0

These bits, in conjunction with bit [13], enable the trace port clocking mode to be set. See Trace port clocking modes.

[15:14]

ContextIDsize

v1.2

The possible values of this field are:

b00

No Context ID tracing.

b01

Context ID bits [7:0] traced.

b10

Context ID bits [15:0] traced.

b11

Context ID bits [31:0] traced.

Note

Only the number of bytes specified is traced even if the new value is larger than this.

From ETMv1.2, these bits Read-as-Zero if Context ID tracing is not supported.

On an ETM reset these bits are zero.

[13]

Half-rate clocking

v1.2    up to v2.1  

This bit controls whether trace is captured off both edges of TRACECLK or only the rising edge. See Trace port clocking modes.

On an ETM reset this bit is 0.

Port mode[2]v3.0

This bit enables the trace port clocking mode to be set in conjunction with bits [17:16]. See Trace port clocking modes.

On an ETM reset this bit is 0.

[12]

Cycle-accurate tracing

v1.0

When set to 1, a precise cycle count of executed instructions can be extracted from the trace. In ETMv1 and ETMv2, this is achieved by causing trace to be captured on every cycle when TraceEnable is active. In ETMv3, this is achieved by adding extra information into the trace, giving cycle counts even when TraceEnable is inactive.

On an ETM reset this bit is 0.

[11]

ETM port selection

v1.0

This bit controls the external ETMEN pin. The possible values are:

0

ETMEN is LOW.

1

ETMEN is HIGH.

This bit must be set by the trace software tools to ensure that trace output is enabled from this ETM. See also Restrictions on the use of the ETMEN signal.

ETMEN can be used to enable the trace port pins to be shared with GPIO pins under the control of logic external to the ETM.

On an ETM reset this bit is 0.

[10]

ETM programming

v1.0

When set to 1, the ETM is being programmed. See ETM Programming bit and associated state.

On an ETM reset this bit is set to b1.

[9]

Debug request control

v1.0

When set to 1 and the trigger event occurs, the DBGRQ output is asserted until DBGACK is observed. This enables the ARM processor to be forced into Debug state.

If the Programming bit is set or the OS Lock is set after the ETM requests the processor to enter debug state but before the processor enters debug state, it is implementation defined whether the ETM sustains this request. The processor might or might not enter debug state.

On an ETM reset this bit is 0.

[8]

Branch output

v1.0

When set to 1 all branch addresses are output, even if the branch was because of a direct branch instruction. Setting this bit enables reconstruction of the program flow without having access to the memory image of the code being executed.

On an ETM reset this bit is 0.

This bit is not supported by all ETMs. From ETMv2.0, if unsupported, this bit ignores writes and Reads-As-Zero.

[7]

Stall processor

v1.0

The FIFOFULL output can be used to stall the processor to prevent overflow. This signal is only enabled when the stall processor bit is set to 1. When this bit is 0 the FIFOFULL output remains LOW at all times and the FIFO overflows if there are too many trace packets.

On an ETM reset this bit is 0.

For information about the interaction of this bit with bit [18] see Processor stalling, FIFOFULL.

If the FIFOFULL signal is not implemented then this bit reads as zero and ignores writes.

[6:4]

Port size [2:0]

v1.0

The port size determines how many external pins are available to output the trace information. In ETMv1 and ETMv2 the port size is the number of bits in TRACEPKT. In ETMv3 the port size is the number of bits in TRACEDATA. This configuration determines how quickly the trace packets are extracted from the FIFO.

From ETMv3 the port size field is 4 bits wide and bits [6:4] must be used in conjunction with bit [21], so that the port size encoding is given by bits [21, 6:4].

See ETM port size encoding for the encoding of these bits.

On an ETM reset these bits correspond to the lowest supported port width.

[3:2]

Data access

v1.0

The possible values of this field are:

b00

No data tracing.

b01

Trace only the data portion of the access.

b10

Trace only the address portion of the access.

b11

Trace both the address and the data of the access.

On an ETM reset these bits are b00.

[1]

MonitorCPRT

v1.0

When 0, the CPRTs are not traced. When set to 1, the CPRTs are traced.

On an ETM reset this bit is 0.

From ETMv2.1, if CPRT tracing is not supported then this bit reads back as 0.

From ETMv.3.0, this bit is used with bit [19]. See Filter Coprocessor Register Transfers (CPRT) in ETMv3.0 and later

[0]

ETM power down

v1.0

A pin controlled by this bit enables the ETM power to be controlled externally. The external pin is often ETMPWRDOWN or inverted as ETMPWRUP. This bit must be cleared by the trace software tools at the beginning of a debug session.

When this bit is set to 1, the ETM must be powered down and disabled, and then operated in a low power mode with all clocks stopped.

When this bit is set to 1, writes to some registers and fields might be ignored. You can always write to the following registers and fields:

  • ETMCR bit [0] and bits [27:25]

  • ETMLAR

  • ETMCLAIMSET register

  • ETMCLAIMCLR register

  • ETMOSLAR.

When the ETMCR is written with this bit set to 1, bits other than bit [0] and bits [27:25] might be ignored.

On an ETM reset this bit is set to 1.

[a] The first ETM architecture version that defines the field, or (where the use of a field is different in different versions) the first architecture version to which the description applies.


Additional information on the ETMCR

The following sections give additional information about fields of the ETMCR:

Note

The debug tools must read back the ETMCR after modification, to confirm that writes were successful. In particular:

  • If you select a port width that is not supported by an ETM configuration, the closest supported size is selected (ETMv1.x and ETM2.x only). In ETMv3.x and later selection of an unsupported port size results in invalid trace.

  • The branch output bit is not supported by all ETM versions. If this bit is not supported, it is 0 when read back.

ETM port size encoding

Table 3.6 shows the encoding of the ETM port size in the ETMCR:

  • from ETMv3.0 the port size is encoded in register bits [21, 6:4]

  • before ETMv3.0 the port size is encoded in register bits [6:4] only.

Table 3.6. ETM port size

Register bits [21, 6:4] [a]Register bits [6:4] [b]Port sizeAvailable [c] in ETM versions:
b0000b0004 bitAll
b0001b0018 bitAll
b0010b01016 bitAll
b0011b01124 bit[d]From ETMv3.0
b0100b10032 bit[d]From ETMv3.0
b0101b10148 bit[d]From ETMv3.0
b0110b11064 bit[d]From ETMv3.0
b0111b111ReservedAll
b1000-1 bitFrom ETMv3.0
b1001-2 bitFrom ETMv3.0
b101X-ReservedFrom ETMv3.0
b110X-ReservedFrom ETMv3.0
b1110-User defined 1From ETMv3.0
b1111-User defined 2From ETMv3.0

[a] Encoding used from ETMv3.0.

[b] Encoding used before ETMv3.0.

[c] An ETM implementation might not support all available encodings. See the information in this section.

[d] Reserved in ETM versions earlier than ETMv3.0.


Not all port sizes are supported by all implementations. You can determine which port sizes are supported from the Maximum port size bits of the ETMSCR, register 0x005. See System Configuration Register, ETMSCR, ETMv1.2 and later.

Restrictions on the use of the ETMEN signal

You must not use the ETMEN signal to gate the ETM clock or any other functionality required for basic operation. The ETMEN signal can be used to control functionality that is only required for off-chip tracing, such as multiplexing between two ETMs. Use the ETMPWRDOWN signal to control basic operation of the ETM.

Checking for implementation defined features, from ETMv3.3

From ETMv3.3, a number of ETM features become implementation defined, and debug tools can write and read the ETMCR to check whether an ETM macrocell supports these features. Table 3.7 summarizes where these checks are described.

Table 3.7. ETMCR checks for implementation defined features

ETM featureETMCRFor more information, see:
Data tracing optionsBits [20:18, 3:1]Checking available data tracing options, ETMv3.3 and later
Data suppression supportBit [18]Checking whether data suppression is supported, in ETMv3.3 and later
Cycle-accurate tracing supportBit [12]Checking support for cycle-accurate tracing, ETMv3.3 and later

Checking whether data suppression is supported, in ETMv3.3 and later

From ETMv3.3, it is implementation defined whether an ETM macrocell supports data suppression. Tools can write and then read the ETMCR to find whether data suppression is supported.

To avoid changing other ETM control settings, the test process is:

  1. Read the ETMCR.

  2. In the returned data, set bit [18], the Suppress data bit, to 1.

  3. Write the modified value back to the ETMCR.

  4. Read the ETMCR again, and check the value of bit [18].

  5. Write the original value, from stage 1, back to the ETMCR.

Checking bit [18] of the register value returned at stage 4 of the test indicates whether data suppression is supported. Table 3.8 shows the possible results.

Table 3.8. Testing whether data suppression is supported, in ETMv3.3 and later

ETMCR bit [18]Data suppression option
1Data suppression supported
0Data suppression not supported

Note

From ETMv3.3, the data tracing options provided by an ETM macrocell are implementation defined. If a macrocell provides none of the optional data trace features then data suppression is not supported, and bit [18] of the ETMCR reads-as-zero. For more information see Data tracing options, ETMv3.3 and later.

Restriction if FIFOFULL and data suppression are both implemented

If an ETM implements both FIFOFULL and data suppression, then only one of these features can be active at any one time. This means that there are restrictions on the permitted values of bits [18, 7] in the ETMCR. These are shown in Table 3.9.

Table 3.9. Permitted Suppress data and Stall processor settings, ETMCR

ETMCREffect
Bit [18] [a]Bit [7] [b]
00FIFOFULL processor stalling and data suppression both disabled.
01FIFOFULL processor stalling enabled, data suppression disabled.
10FIFOFULL processor stalling disabled, data suppression enabled.
11

Prohibited combination. ETM behavior is unpredictable.

[a] Suppress data bit.

[b] Stall processor bit (FIFOFULL).


Note

  • If an ETM implementation does not support one of these features then it ignores any write to the corresponding bit of the ETMCR. For example, if an implementation does not support FIFOFULL processor stalling then the ETM ignores any write to bit [7] of the ETMCR.

  • FIFOFULL processor stalling requires support by the connected processor. See Processor stalling, FIFOFULL.

Checking support for cycle-accurate tracing, ETMv3.3 and later

From ETMv3.3, whether cycle-accurate tracing is defined is implementation defined, and debug tools can write and then read the ETMCR to find whether cycle-accurate tracing is supported. To avoid changing other ETM control settings, the test process is:

  1. Read the ETMCR.

  2. In the returned data, set bit [12], the Cycle-accurate tracing bit, to 1.

  3. Write the modified value back to the ETMCR.

  4. Read the ETMCR again.

Checking bit [12] of the register value returned at stage 4 of the test indicates whether data suppression is supported. Table 3.10 shows the possible results.

Table 3.10. Testing whether cycle-accurate tracing is supported, ETMv3.3 and later

ETMCR bit [12]Data suppression option
1Cycle-accurate tracing supported
0Cycle-accurate tracing not supported

Checking available data tracing options, ETMv3.3 and later

From ETMv3.3, it is implementation defined whether the following data trace options are available:

  • data address tracing

  • data value tracing

  • CPRT tracing

  • data-only mode.

These options are not independent. See Data tracing options, ETMv3.3 and later for details of the permitted implementations.

Debug tools can find out which data tracing options are implemented by writing to the ETMCR with the appropriate bits set to one, and then reading the register back to see whether those bits have been set. To avoid changing other ETM control settings, the test process is:

  1. Read the ETMCR.

  2. Set the following bits or fields in the returned data:

    • bit [1], the Monitor CPRT bit, to 1

    • bits [3:2], the Data access field, to b11

    • bit [18], the Suppress data bit, to 1

    • bit [19], the Filter CPRT bit, to 1

    • bit [20], the Data-only mode bit, to 1.

  3. Write the modified value back to the ETMCR.

  4. Read the ETMCR again.

Bits [21:18, 3:1] of the register value returned at stage 4 of the test indicate which data tracing features are implemented. Table 3.11 shows the values that can be returned.

Table 3.11. Testing which data tracing features are implemented, ETMv3.3 and later

ETMCRData address tracingData value TracingCPRT tracingData-only mode
Bits [20:18]Bits [3:1]
b11Xb111Full implementation, all data tracing features are implemented
b00Xb100ImplementedNot implementedNot implementedNot implemented
b01Xb011Not implementedImplementedImplementedNot implemented
b000b000Not implementedNot implementedNot implementedNot implemented

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