2.2.1. Memory access resources

There are the following types of memory access resource:

Single address comparators

Address comparators compare either the instruction address or the data address against a user-programmed value. There are between zero and 16 single address comparators, but there must be an even number of them. Each pair can have an associated bit-masked data value comparator. See Data value comparators.

Each comparator has several configuration bits to determine the match conditions. The available options are:

  • instruction fetch

  • instruction execute, irrespective of condition code passed or failed

  • instruction executed and condition code test passed, in ETMv1.2 or later

  • instruction executed and condition code test failed, in ETMv1.2 or later

  • data load or store

  • data load only

  • data store only.

Note

From ETMv3.3, an ETM implementation might not support data address comparisons. See No data address comparator option, ETMv3.3 and later for more information.

Instruction execute means that the instruction at that address has reached the Execute stage of the pipeline and includes instructions that fail their condition codes. ETMv1.2 introduced the facility to control trace using the result of the condition code test whenever an instruction is executed.

The address comparators are not bit-masked. This means that you cannot use a single comparator to generate a binary range (starts at an offset of 0 and ends at an offset of 2n). If a range is required, you must use one of the following:

  • A pair of comparators configured for address range comparison. See Address range comparators.

  • The implementation specific memory map decoders described in Memory map decoder (MMD).

  • The ARM EmbeddedICE module. This is only available in processors supporting the RANGEOUT signal, and enables you to carry out full masked address comparisons using a single EmbeddedICE comparator.

Typically, a single address comparator only matches for a single cycle, regardless of its configuration. This ensures that counter and sequencer transitions occur cleanly, without the possibility of multiple counts or transitions from, for example, memory wait states. For more information see Address comparators.

The 32-bit address from the ARM processor, that might have bits [1:0] masked depending on whether these bits can be safely predicted, is compared with the address value.

In ETMv2.0 and later, you can make address comparators conditional on a Context ID comparator matching. Every Context ID comparator is available to every address comparator for use in this way.

In ETMv3.2 and later, with a processor that supports the Security Extensions, you can configure the comparator to match only in the Secure state, only in the Non-secure state, or in both Secure and Non-secure states.

In ETMv3.5, you can configure comparator matching to depend on the current processor mode.

In ETMv3.5, with a processor that supports the Virtualization Extensions, you can configure the comparator matching to depend on:

  • whether the processor is in Hyp mode

  • the value of the Virtual Machine ID (VMID).

If you use a comparator with the Exact match bit set to 1 in the programming of TraceEnable or ViewData, tracing is Imprecise. See Exact matching, in ETMv2.0 and later for more information.

Address range comparators

The single address comparators are arranged in pairs to form an address range resource. An address range comparator is programmed as follows:

  • the first comparator is programmed with the range start address

  • the second comparator is programmed with the range end address.

  • the second comparator value must be greater than the first comparator value.

The resource matches if the address is in the following range:

(address >= range start address) AND (address < range end address)

An address range comparator can operate on instruction or data addresses.

unpredictable behavior occurs if the two address comparators are not configured in the same way. For example, behavior is unpredictable if one comparator is configured to match on instruction fetch and the other is configured to match on instruction execute.

Features such as out of range are dealt with using:

Note

From ETMv3.3, an ETM implementation might not support data address comparisons. See No data address comparator option, ETMv3.3 and later for more information.

Typically, an address range resource matches for a continuous number of cycles. The match first occurs when the address is in the correct range. The comparator remains in this state until a new address outside the matching range is generated. Any access outside the matching range causes the comparator to go inactive. For more information see Address comparators.

No data address comparator option, ETMv3.3 and later

From ETMv3.3, it is implementation defined whether an ETM macrocell supports data address comparisons. Support for data address comparisons is indicated by bit [12] of the ETMCCER. See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later. This bit is set to 1 if data address comparisons are not supported. This means that, from ETMv3.1, this bit can be checked to see if data address comparisons are supported. If reading the ETMCCER returns bit [12] = 0 then data address comparisons are supported.

If an implementation does not support data address comparisons:

  • Setting the Access type field, bits [2:0], of an ETMACTR to a data operation causes unpredictable behavior. See Address Comparator Access Type Registers, ETMACTRn.

  • Data value comparators are not supported:

    • The Number of data value comparators field, bits [7:4], of the ETMCCR returns a value of b0000. See Configuration Code Register, ETMCCR.

    • The ETMDCVRs and ETMDCMRs are not implemented and Read-As-Zero. These are registers 0x030 to 0x04F, at addresses 0x0C0-0x13C in a memory-mapped implementation.

    Note

    The ETM architecture permits an implementation to support data address comparisons even if it does not implement any data value comparators.

Data value comparators

Each pair of address comparators can be associated with a specific data value comparator. An address comparator that has an associated data value comparator also has a data value comparison enable field.

A data value comparator monitors the data bus only when a load or store operation occurs.

Data value comparisons are not supported for address comparators configured for instruction addresses. unpredictable behavior results if a data value comparison is enabled for an instruction Fetch or Execute comparator.

The number of data value comparators is implementation defined. Between zero and eight address comparator pairs can have associated data value comparators. About the data value comparator registers describes exactly how data value comparators must be allocated to the address comparators.

A data value comparator has both a value register and a mask register, so it is possible to compare only certain bits of the pre-programmed value against the data bus.

For information on data value comparisons during aborts, see Exact matching, in ETMv2.0 and later.

An address comparison, or address range comparison, is qualified by the data value comparison.

ETMv1.2 and later also supports matching if the data value comparison does not match.

The behavior of the comparators for data value comparisons, for all ETM versions, is described in Operation of data value comparators.

Context ID comparators

In ETMv2.0 and later, you can use Context ID comparators for trace filtering. Each has a 32-bit value register, and one mask register is shared between all Context ID comparators. Context ID comparators can be used directly by address comparators, or selected as part of an event. There are between zero and three Context ID comparators. For more information, see About the Context ID comparator registers, ETMv2.0 and later.

Virtual Machine ID comparator

In ETMv3.5, you can use the Virtual Machine ID comparator for trace filtering. The comparator has an 8-bit value register, used to compare with the current Virtual Machine ID. The Virtual Machine ID comparator can be used directly by address comparators, or selected as part of an event. See Filtering by state and mode, in ETMv3.5.

EmbeddedICE watchpoint comparators

You can use the EmbeddedICE module watchpoint comparators as additional trigger resources.

Note

  • This resource is not available in all implementations. For example, it is not available on ETMs for the ARM10 and ARM11 product families, because these processors do not have the RANGEOUT output.

  • EmbeddedICE comparators are architecturally defined in all versions of the ETM architecture, even though some ETMs do not implement them.

In ETMv3.3 and earlier, if an ETM implements EmbeddedICE watchpoint comparator inputs then it provides two inputs. These correspond to the RANGEOUT[1:0] signals, that are available from ARM7 and ARM9 processors only.

From ETMv3.4, the number of EmbeddedICE watchpoint comparator inputs is implementation defined, in the range 0 to 8. For more information about the implementation of EmbeddedICE watchpoint comparator inputs in ETMv3.4 and later, see Behavior of EmbeddedICE inputs, from ETMv3.4.

Memory map decoder (MMD)

Some system designs contain an address decoder that divides the memory space statically into different regions. For example, the MMD might divide the memory into separate regions for RAM, ROM, and peripherals. For these systems, you can customize the ETM with external logic for a particular application, to enable low-cost decoding of address regions.

Note

  • The MMD is not available in all implementations. When an ETM does not implement an MMD you can use the EXTIN inputs as an imprecise tracing alternative. For more information, see External inputs.

  • MMDs are architecturally defined in all versions of the ETM architecture, even though some ETMs do not implement them.

As with the full address comparator resources, up to 16 MMDs are supported. An additional control register enables you to configure statically the memory decode map to be used.

The interface to the external Memory Map Decode (MMD) logic is implementation specific. See the appropriate Technical Reference Manual for more information.

The MMD behaves in a similar way to the address range comparators, except that the MMD always uses the full 32-bit address, and you must implement any masking of addresses externally.

The instruction and data addresses that the decoder operates on are registered. The MMD becomes active when the address first matches, and remains active until the comparison fails.

If precise memory comparisons are required, you must ensure that the match is active only for a single cycle. This ensures that the behavior is identical to the full address comparators described earlier in this section. See Single address comparators.

The comparisons are likely to be simple bit-masked comparisons. This behavior is similar to that of a typical memory decoder present in the ASIC memory system. The hardware required to implement this is minimal.

Memory map decoding is only possible as Fetch stage comparisons. No attempt is made to produce or select Execute stage versions. You are likely to use these resources primarily to decode the peripheral address map, and possibly to subdivide the ARM processor code and data space. ViewData is precise when based on memory map data address comparisons resources. See ViewData and filtering the data trace.

For a Harvard ARM processor, that is, one with separate instruction and data memory interfaces, the designer of the memory map decoder must choose one of the following decode strategies:

  • Apply the same decode map to both the instruction and data address buses.

  • Decode the instruction and data address buses separately.

    This is preferable because, for example, instructions are never fetched from the peripheral memory space.

The exact MMD map is implementation specific. At any one time there are only 16 memory map resources available. Many ASICs have a more complex memory map than this, so the ETMASICCR, register 0x003, can be used to configure the MMD logic. For example, you can use this register to switch between instruction address and data address decoding. You are unlikely to use more than one or two bits of this register for this purpose.

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