5.6.2. Full address output

For large trace captures it is necessary to periodically output a full 32-bit address so that the trace can be correctly decompressed.

A cycle counter is implemented. When this counter reaches its maximum count of 1024 a full address is output, for an indirect branch, at the next opportunity, provided that the FIFO can accept the five trace packets required without overflowing. If this is not possible then the branch is treated normally. This process continues for up to 512 cycles until there is enough space in the FIFO to accept a full 32-bit address. The ETM resets the counter whenever a full address is generated.

If there are no indirect branches (such as in a large program loop), or there is insufficient space in the FIFO, a full address is not generated. In this case a full 5-packet address is forced by either:

Both of these measures can cause an overflow to occur. However, this drawback is a reasonable penalty for ensuring synchronization.

ETMv1.2 or later assigns a reason code of b100 to these full addresses. ETMv1.0 and ETMv1.1 use reason code b000.

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