3.5.2. Configuration Code Register, ETMCCR

The ETMCCR characteristics are:

Purpose

Enables software to read the implementation defined configuration of the ETM, giving the number of each type of resource. Where a value indicates the number of instances of a particular resource, zero indicates that there are no implemented resources of that resource type.

Usage constraints

There are no usage constraints.

Configurations

This register is available in all ETM implementations.

Attributes

See the register summary in Table 3.3, and Reset behavior.

Figure 3.5 shows the ETMCCR bit assignments for architecture version 3.1 and later, and Figure 3.6 shows the bit assignments for architecture versions 1.x. See Table 3.12 for the differences in other architecture versions.

Figure 3.5. ETMCCR bit assignments, from architecture v3.1

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Figure 3.6. ETMCCR bit assignments for architecture v1.x

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Table 3.12 shows the ETMCCR bit assignments, and describes how these are different for different versions of the ETM architecture.

Table 3.12. ETMCCR bit assignments

Bits

Max. value

Version [a]

Description

[31]

1All

When set to 1, this bit indicates that the ETMIDR, register 0x79, is present and defines the ETM architecture version in use. When set to 0, this bit indicates that the ETMIDR is not present. For more information, see ID Register, ETMIDR, ETMv2.0 and later.

[30:28]

-v2.0

Reserved.

For ETMv2.0 and later the ETM architecture version is given in the ETMIDR. See ID Register, ETMIDR, ETMv2.0 and later.

7v1.x onlyProtocol version, when ETMIDR not present.

[27]

1

v3.1

Coprocessor or memory-mapped access to registers supported. See Programming and reading ETM registers.

[26]

1v2.0

When set to 1, the trace start/stop block is present.

In ETMv1.2 and ETMv1.3, the trace start/stop block is always present and this bit is Read-As-Zero.

[25:24]

3

v2.0

Number of Context ID comparators.

[23]

1v1.0

When set to 1, the FIFOFULL logic is present. This bit is used in conjunction with bit [8] of the System Configuration Register of the processor connected to the ETM.

Note

You can use FIFOFULL only if it is supported by both your ETM and your system. Some processors do not support FIFOFULL, so it cannot be used by the system.

If this bit is 0, the ETMFFRR, register 0x00A, is not implemented and is Reserved, RAZ. In this case, the Processor stall bit, bit [7], of the ETMCR might ignore writes.

[22:20]

4

v1.0

Number of external outputs. Supplied by the ASIC in ETMv3.1 and later.

[19:17]

4

v1.0

Number of external inputs. Supplied by the ASIC in ETMv3.1 and later.

[16]

1

v1.0

When set to b1the sequencer is present.

[15:13]

4

v1.0

Number of counters.

[12:8]

16

v1.0

Number of memory map decoder inputs.

If this bit is 0, the ETMVDCR2, register 0x00E, is not implemented and is Reserved, RAZ.

[7:4]

8

v1.0

Number of data value comparators.

From ETMv3.3, this field is zero if data address comparisons are not supported. See No data address comparator option, ETMv3.3 and later for more information.

[3:0]

8

v1.0

Number of pairs of address comparators.

[a] The first ETM architecture version that defines the field, or (where the use of a field is different in different versions) the first architecture version to which the description applies.


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