3.5.4. ASIC Control Register, ETMASICCR

The ETMASICCR characteristics are:

Purpose

Controls ASIC logic, such as the static configuration of Memory Map Decoders (MMDs).

Usage constraints

Support of this register is implementation defined, and tools cannot detect whether this register is implemented. Writing to this register has no effect if it is not implemented.

Configurations

This is an optional register in implementations that do not implement any MMDs.

This register was previously called the Memory Map Decoder Register.

Attributes

See the register summary in Table 3.3, and Reset behavior.

Figure 3.8 shows the ETMASICCR bit assignments.

Figure 3.8. ETMASICCR bit assignments

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Table 3.14 shows the ETMASICCR bit assignments.

Table 3.14. ETMASICCR bit assignments

Bits

Defined in ETM architecture versions

Description

[31:n+1]-Reserved

[n:0]

v1.0 and later

ASIC control

The size of this field is implementation defined, but is usually eight bits


The ETM outputs the value of this register to the ASIC logic over a dedicated bus. This can be used for many purposes, but its intended use is to refine memory map decoders. See Memory map decoder (MMD).

Even where MMDs are not supported by the ETM, sometimes the tools are required to be able to communicate with the ASIC in a general manner, in addition to the special-purpose bits defined in the ETMCR, see Main Control Register, ETMCR. You can use the ETMASICCR for this communication.

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