3.5.12. Controlling FIFO overflow using the FIFOFULL registers

ETM includes control of FIFO overflow by implementing a signal, FIFOFULL, that it asserts when the FIFO is close to overflow, and two registers that control the assertion of this signal. The following sections describe these FIFOFULL registers:

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211