3.5.31. About the sequencer registers

An ETM implementation can include a sequencer. If it does, a debugger controls the sequencer by defining the events that cause the sequencer to move between the different states.

Each sequencer state transition event has its own register, and these registers are programmed to control the state transitions. An additional register holds the current state of the sequencer. Table 3.41 lists the sequencer registers, with the register number and address offset of each register.

When programming the sequencer, you must program a valid encoding into each ETMSQabEVR, otherwise the behavior of the sequencer is unpredictable. For example, if you want the sequencer only to involve transitions between states 1 and 2, you must:

It is implementation defined whether the sequencer state is reset to 1 when any of the ETMSQabEVR registers are programmed.

From ETMv3.1, if the sequencer must be in a particular state when the ETM Programming bit is cleared, you must write ETMSQR after programming the ETMSQabEVR Registers to ensure this value is used. Otherwise the sequencer state resets to 1 when the ETM Programming bit is cleared.

Prior to ETMv3.1, ETMSQR is read-only and the sequencer state always resets to 1 when the ETM Programming bit is cleared.

Table 3.41. Sequencer register allocation

RegisterTypeVersion [a]

Description

NumberOffset [b]
0x060

0x180

WO[c]

v1.0

State 1 to State 2 Transition Event Register, ETMSQ12EVR [d]

0x061

0x184

WO[c]

v1.0

State 2 to State 1 Transition Event Register , ETMSQ21EVR[d]

0x062

0x188

WO[c]

v1.0

State 2 to State 3 Transition Event Register , ETMSQ23EVR[d]

0x063

0x18C

WO[c]

v1.0

State 3 to State 1 Transition Event Register , ETMSQ31EVR[d]

0x064

0x190

WO[c]

v1.0

State 3 to State 2 Transition Event Register , ETMSQ32EVR[d]

0x065

0x194

WO[c]

v1.0

State 1 to State 3 Transition Event Register, ETMSQ13EVR[d]

0x066

0x198

-

-

Reserved

0x067

0x19C

RO

v1.0

ETMSQR. See Current Sequencer State Register, ETMSQR

RWv3.1

[a] The first ETM architecture version that defines the field, or the first architecture version to which the Type description applies.

[b] When the registers are accessed in a memory-mapped scheme, the register offset is always (4 x (Register number)).

[c] In ETMv3.1 and later, these bits are read-write if bit [11] of the ETMCCER is set to 1. See Configuration Code Extension Register, ETMCCER, ETMv3.1 and later.

[d] See Sequencer State Transition Event Registers, ETMSQabEVR for a description of this register.


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