3.5.5. ETM Status Register, ETMSR, ETMv1.1 and later

The ETMSR characteristics are:


Provides information about the current status of the trace and trigger logic.

Usage constraints

The access type depends on the ETM version. See the register summary in Table 3.3.


Only implemented in ETMv1.1 and later.


See the register summary in Table 3.3, and Reset behavior.

Figure 3.9 shows the ETMSR bit assignments, for ETM architecture version 3.1 and later. See Table 3.15 for the differences in other architecture versions.

Figure 3.9. ETMSR bit assignments for architecture v3.1

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Table 3.15 shows the ETMSR bit assignments, and describes the differences between different ETM architecture versions.

Table 3.15. ETMSR bit assignments


Type [a]Version [b]



Trigger bit.

Set when the trigger occurs, and prevents the trigger from being output until the ETM is programmed again. This bit exists in all architecture versions, but can only be accessed in ETMv3.1 and later as described in ETM Programming bit and associated state.


ROv1.2 to v3.0

Holds the current status of the trace start/stop resource. If set to 1, it indicates that a trace on address has been matched, without a corresponding trace off address match.




The current effective value of the ETM Programming bit, bit [10] of the ETMCR. You must wait for this bit to go to 1 before you start to program the ETM as described in ETM Programming bit and associated state.

If you read other bits in the ETMSR while this bit is 0, some instructions might not have taken effect. ARM recommends that you set the ETM Programming bit and wait for this bit to go to 1 before reading the overflow bit.

In ETMv3.2 and later this bit remains 0 if there is any data in the FIFO. This ensures that the FIFO is empty before the ETM programming is changed.

In ETMv3.5 this bit is set when the OS Lock is set. See OS Lock Status Register, ETMOSLSR, ETMv3.3 and later.

In ETMv3.5 this bit must be polled before saving or restoring state. See Access permissions for ETMv3.5, multiple power domains



If set to 1, there is an overflow that has not yet been traced. This bit is cleared to 0 when either:

  • trace is restarted.

  • the ETM Power Down bit, bit [0] of ETMCR, is set to 1.


Setting or clearing the ETM Programming bit does not cause this bit to be cleared to 0.

[a] In architecture versions before 3.1, all fields in the register are RO.

[b] The first ETM architecture version that defines the field, or (where the use of a field is different in different versions) the first architecture version to which the description applies.

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