3.4.2. Reset behavior

This document describes the following resets, or reset operations:

Processor reset

This resets the processor, making it start execution from the reset vector address. This does not reset any ETM registers. The ETM indicates the processor reset by inserting an exception packet in the trace stream. The branch address in the exception packet indicates that the exception was a processor reset.

ETM reset

This resets all resettable ETM registers, as defined by the register descriptions. This is the main reset for the entire ETM.

TAP reset

In an ETM that supports Direct JTAG connection, this resets the TAP controller:

  • in ETMv3.0 and earlier, this might also perform an ETM reset

  • from ETMv3.1, this might not reset any ETM registers.

Power-on reset

Whether an ETM supports a power-on reset is implementation defined. If it is supported, a power-on reset must perform an ETM reset. If the ETM supports Direct JTAG connection it must also perform a TAP reset.

Writing to the Programming bit

Writing to the Programming bit of the ETMCR is a reset operation that resets parts of the ETM to their ETM reset state. You reset some parts of the ETM by writing a 1 to this bit, and reset other part by writing 0 to this bit. For more information see ETM Programming bit and associated state.

On an ETM reset, the state of the ETMCR is set to the state described in Table 3.5. In particular, the power-down bit and the Programming bit are set to 1. See ETM Programming bit and associated state.

Moving the TAP state machine into Test-Logic Reset state resets only the TAP controller. No ETM registers are affected. To prevent unpredictable ETM behavior, a TAP reset must be asserted when the ETM is initially powered on.

In ETMv3.1 and later, a TAP reset might not reset the ETM registers because this might be done by a power-on reset, depending on the processor reset methodology. See the appropriate Technical Reference Manual for more information. You can achieve the same effect by writing the reset value to the ETMCR, register 0x000.

On an ETM reset, the status of registers or individual bits is unknown where not specified.

Note

See ETM Programming bit and associated state for a description of how the value of the Programming bit affects these registers.

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