2.6.6. Preventing FIFO overflow

When a FIFO overflow occurs, tracing is suspended until the contents of the FIFO have been drained. The resulting gap in the trace is marked, but a large number of overflows can affect the usefulness of the trace.

FIFO overflows are usually the result of large quantities of data tracing combined with a narrow trace port. You can try the following if you experience a large number of overflows:

Note

Frequent toggling of TraceEnable can increase the number of overflows. This is because of the large amount of extra trace produced at the beginning of each trace region to ensure synchronization. ARM recommends that you do not disable tracing unless it is switched off for a significant number of cycles. See Programming strategies for more information.

In addition, the ETM can support one or both of the following mechanisms to reduce the likelihood of overflow:

Data suppression is generally the more effective mechanism. At the time of writing, no ETM implementation supports both options. If both mechanisms are implemented, only one can be enabled at any time.

Processor stalling, FIFOFULL

Processor stalling causes the processor to be stalled when the FIFO is close to overflow. This affects the performance of the system. Where supported, an output called FIFOFULL indicates to the processor when to stall.

Processor stalling requires support from both the ETM and the system. Most processors for ETMs supporting FIFOFULL have a FIFOFULL input, but some, such as the ARM7TDMI™ processor, require support to be built into the memory system to stall the processor. See the Technical Reference Manuals for your processor and your ETM for more information. Therefore there are two bits to indicate support:

  • A bit in the ETMCCR, register 0x001, indicates whether the ETM supports FIFOFULL. See Configuration Code Register, ETMCCR.

  • A bit in the System Configuration Register of the processor indicates whether the system supports FIFOFULL. See the description of the System Configuration Register in the Technical Reference Manual for your processor.

Figure 2.10 shows the generation of the FIFOFULL signal.

Figure 2.10. FIFOFULL generation

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


You configure the FIFOFULL logic by programming the FIFO overflow registers as Figure 2.11 shows. For more information, see Controlling FIFO overflow using the FIFOFULL registers.

Figure 2.11. Programming the FIFOFULL logic

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Some implementations of ETMv2.0 and later might ignore the recommended minimum byte count, and instead assert FIFOFULL (if enabled) whenever any bytes are present in the FIFO. This means that the ETM can respond earlier in the ETM pipeline, reducing the chance of overflow.

The FIFOFULL signal is a request to the processor for it to halt as soon as possible until FIFOFULL is deasserted. It can take several cycles for the processor to respond to a FIFOFULL signal, so in some systems the use of FIFOFULL cannot eliminate overflows entirely.

Several early revisions of ARM processors have no support for an additional stall signal. The memory system usually asserts nWAIT to stall the processor, based on address-based wait states or bus arbitration. In these cases you must design the FIFOFULL stall signal into the system because it is at this level that the stalling occurs. To establish whether your ARM processor has a FIFOFULL input, see the Technical Reference Manual for your processor.

You must consider the effect of FIFOFULL on interrupt latency. If the assertion of FIFOFULL causes a load or store multiple (LSM) instruction to be delayed, an IRQ or FIQ is not taken until the delayed instruction completes. This means that the worst-case interrupt latency can be affected. You can configure some processors, such as the ARM966E-S (Rev 1) and ARM926EJ-S (Rev 0) processors, to ignore FIFOFULL when interrupts occur. See the Technical Reference Manual for your processor to find out if it supports this feature.

Processor stalling takes several cycles to take effect. After FIFOFULL is asserted there is a delay before the processor is stalled, and there can be an additional delay while trace that has already entered the ETM pipeline enters the FIFO. The ETMFFLR must take account of this.

Depending on the size of the FIFO and the processor in use, the delay can mean that some overflows still occur regardless of the value of the ETMFFLR. In particular, some processors are only able to stall on instruction boundaries. This reduces the effectiveness of FIFOFULL on long LSMs.

FIFO overflow is independent of all resource matching, events, and sequencer state changes. No ETM resources are affected by a FIFO overflow.

Data suppression

Data suppression causes data tracing to be disabled when the FIFO is close to overflow. This does not affect the performance of the system.

Instruction tracing is unaffected. Because the bandwidth required for instruction trace is generally far lower than the bandwidth required for data trace, data suppression is normally highly successful in preventing overflow. The resulting gaps in the data trace are marked in the signal protocol.

For more information on the effect of data suppression on the trace, see Data suppressed packet.

Data suppression is only available from ETMv3.0:

If an implementation supports both FIFOFULL processor stalling and data suppression, the two features must not be enabled at the same time. See Restriction if FIFOFULL and data suppression are both implemented.

A minimum empty byte count is provided to specify the point below which the FIFO is considered full, as Figure 2.12 shows. This setting is made in the ETMFFLR and is shared with the FIFOFULL logic, if present.

Figure 2.12. SuppressData inputs

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


You configure the data suppression logic by programming the ETMFFLR, as Figure 2.13 shows. SuppressData ignores the ETMFFRR, because data suppression cannot be controlled by address regions. An ETM implementation that supports data suppression but does not implement the FIFOFULL logic does not implement the ETMFFRR, but must implement the ETMFFLR.

Figure 2.13. Programming the data suppression logic

To view this graphic, your browser must support the SVG format. Either install a browser with native support, or install an appropriate plugin such as Adobe SVG Viewer.


Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211