3.8.4. Guidelines for the ETM trace registers to be saved and restored

It is implementation defined which registers are included in the save and restore mechanism. However, the mechanism must include all registers whose contents are lost in a power-down. Table 3.95 gives a list of the ETM registers typically included in the save and restore mechanism.

Table 3.95. Typical list of ETM registers to be saved and restored

Register number Register offset Register name
0x000 0x000 Main Control
0x002 0x008 Trigger Event
0x003 0x00C ASIC Control
0x004 0x010 Status
0x006 0x018 TraceEnable Start/Stop
0x007 0x01C TraceEnable Control 2
0x008 0x020 TraceEnable Event
0x009 0x024 TraceEnable Control 1
0x00A 0x028 FIFOFULL Region
0x00B 0x02C FIFOFULL Level
0x00C 0x030 ViewData Event
0x00D 0x034 ViewData Control 1
0x00E 0x038 ViewData Control 2
0x00F 0x03C ViewData Control 3
0x010-0x01F 0x040-0x07C Address Comparator Value 1-16
0x020-0x02F 0x080-0x0BC Address Comparator Access Type 1-16
0x030-0x03F 0x0C0-0x0FC Data Comparator Value 1-16
0x040-0x04F 0x100-0x13C Data Comparator Mask 1-16
0x050-0x053 0x140-0x14C Counter Reload Value 1-4
0x054-0x057 0x150-0x15C Counter Enable 1-4
0x058-0x05B 0x160-0x16C Counter Reload Event 1-4
0x05C-0x05F 0x170-0x17C Counter Value 1-4
0x060-0x065 0x180-0x194 Sequencer Control
0x067 0x19C Sequencer State
0x068-0x06B 0x1A0-0x1AC External Output Event 1-4
0x06C-0x06E 0x1B0-0x1B8 Context ID Comparator Value 1-3
0x06F 0x1BC Context ID Comparator Mask
0x078 0x1E0 Synchronization Frequency
0x07B 0x1EC Extended External Input Selection
0x07C0x1F0TraceEnable Start/Stop EmbeddedICE Control
0x07D0x1F4EmbeddedICE Behavior Control
0x07E0x1F8Timestamp Event
0x07F0x1FCAuxiliary Control
0x080 0x200 CoreSight Trace ID
0x3E80xFA0Claim Tag Set, ETMv3.5
0x3E90xFA4Claim Tag Clear, ETMv3.5

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q