3.10.2. Debugger accesses, ETMv3.3 and ETMv3.4, SinglePower

Table 3.96 shows the behavior of debugger accesses in a SinglePower implementation in ETMv3.3 and ETMv3.4. See ETM state definitions, ETMv3.3 and ETMv3.4, SinglePower for the meanings of the column headings.

Table 3.96. Debugger accesses, ETMv3.3 and ETMv3.4, SinglePower

 ETM state
RegisterNo PowerOtherwise
Trace registersErrorOK[a]
ETMLSRErrorOK/RAZ
ETMLARErrorWI
ETMPDSRErrorOK
ETMOSLSRErrorOK
ETMOSLARErrorOK
ETMOSSRRErrorunp

ETMDEVID, ETMAUTHSTATUS

ErrorOK
Other ManagementErrorOK
Reserved TraceErrorUNK/SBZP
Reserved ManagementErrorUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored


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