3.10.3. Memory-mapped accesses, ETMv3.3 and ETMv3.4, SinglePower

Table 3.97 shows the behavior of memory-mapped accesses in a SinglePower implementation in ETM v3.3 and ETMv3.4. See ETM state definitions, ETMv3.3 and ETMv3.4, SinglePower for the meanings of the column headings.

Table 3.97. Memory-mapped accesses, ETMv3.3 and ETMv3.4, SinglePower

 ETM state 
RegisterNo PowerOtherwise
Trace RegistersErrorOK[a][b]
ETMLSRErrorOK
ETMLAR[c]ErrorOK
ETMPDSRErrorOK
ETMOSLSRErrorOK
ETMOSLARErrorOK[b]
ETMOSSRRErrorunp
ETMDEVID, ETMAUTHSTATUSErrorOK
Other ManagementErrorOK[b]
Reserved TraceErrorUNK/SBZP
Reserved ManagementErrorUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored

[b] When the CS Lock is set, these registers are WI.

[c] ETMLAR is not visible to Debugger accesses, so writes are ignored.


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