3.10.4. Coprocessor accesses, ETMv3.3 and ETMv3.4, SinglePower

Table 3.98 shows coprocessor access permissions for SinglePower implementations in ETM v3.3 and ETMv3.4. See ETM state definitions, ETMv3.3 and ETMv3.4, SinglePower for the meanings of the column headings.

Table 3.98. Coprocessor accesses, ETMv3.3 and ETMv3.4, SinglePower

 ETM state
RegisterNo PowerNon-PrivilegedOtherwise
Trace registersNPossErrorOK[a]
ETMLSRNPossErrorOK/RAZ
ETMLAR[b]NPossErrorWI
ETMPDSRNPossErrorOK
ETMOSLSRNPossErrorOK
ETMOSLARNPossErrorOK
ETMOSSRRNPossErrorunp
ETMDEVID, ETMAUTHSTATUSNPossErrorOK
Other ManagementNPossErrorOK
Reserved TraceNPossErrorUNK/SBZP
Reserved ManagementNPossErrorUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored

[b] ETMLAR is not visible to Debugger accesses, so writes are ignored


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