3.11.2. Debugger accesses, ETMv3.3 and ETMv3.4, multiple power domains

Table 3.99 shows debugger access permissions for full tracing implementations in ETM v3.3 and ETMv3.4. See ETM state definitions, ETMv3.3 and ETMv3.4, multiple power domains for the meanings of the column headings.

Table 3.99. Debugger accesses, ETMv3.3 and ETMv3.4, multiple power domains

 ETM state
RegisterNo Debug PowerNo Core PowerSticky State SetOS Lock SetOtherwise
Trace registersErrorErrorErrorErrorOK[a]
ETMLSRErrorOK/RAZOK/RAZOK/RAZOK/RAZ
ETMLAR[b]ErrorWIWIWIWI
ETMPDSRErrorOKOKOKOK
ETMOSLSRErrorOKOKOKOK
ETMOSLARErrorunpOKOKOK
ETMOSSRRErrorunpunpOKunp
ETMDEVID, ETMAUTHSTATUSErrorOKOKOKOK
Other ManagementErrorOKOKOKOK
Reserved TraceErrorErrorErrorErrorUNK/SBZP
Reserved ManagementErrorUNK/SBZPUNK/SBZPUNK/SBZPUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored.

[b] ETMLAR is not visible to Debugger accesses, so writes are ignored.


Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211