3.11.3. Memory-mapped accesses, ETMv3.3 and ETMv3.4, multiple power domains

Table 3.100 shows memory-mapped access permissions for full tracing implementations in ETM v3.3 and ETMv3.4. See ETM state definitions, ETMv3.3 and ETMv3.4, multiple power domains for the meanings of the column headings.

Table 3.100. Memory-mapped accesses. ETMv3.3 and ETMv3.4, multiple power domains

 ETM state    
RegisterNo Debug PowerNo Core PowerSticky State setOS Lock SetOtherwise
Trace registersErrorErrorErrorErrorOK[a][c]
ETMLSRErrorOKOKOKOK
ETMLARErrorOKOKOKOK
ETMPDSRErrorOK[b]OK[b]OK[b]OK[b]
ETMOSLSRErrorOKOKOKOK
ETMOSLARErrorunpOK[c]OK[c]OK[c]
ETMOSSRRErrorunpunpOK[c]unp
ETMDEVID, ETMAUTHSTATUSErrorOK[c]OK[c]OK[c]OK[c]
Other ManagementErrorOK[c]OK[c]OK[c]OK[c]
Reserved TraceErrorErrorErrorErrorUNK/SBZP
Reserved ManagementErrorUNK/SBZPUNK/SBZPUNK/SBZPUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored.

[b] When the CS Lock is set, reads from the ETMPDSR do not clear the Sticky State.

[c] When the CS Lock is set, these registers are WI.


Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211