3.11.4. Coprocessor accesses, ETMv3.3 and ETMv3.4, multiple power domains

Note

Coprocessor access to these registers is not possible when the core domain is powered down.

Table 3.101 shows coprocessor access permissions for full tracing implementations in ETM v3.3 and ETMv3.4. See ETM state definitions, ETMv3.3 and ETMv3.4, multiple power domains for the meanings of the column headings.

Table 3.101. Coprocessor accesses. ETMv3.3 and ETMv3.4, multiple power domains

 ETM state
RegisterNo Debug PowerNo Core PowerNon- PrivilegedSticky State SetOS Lock SetOtherwise
Trace registersErrorNPossErrorErrorErrorOK[a]
ETMLSRErrorNPossErrorOK/RAZOK/RAZOK/RAZ
ETMLAR[b]ErrorNPossErrorWIWIWI
ETMPDSRErrorNPossErrorOKOKOK
ETMOSLSRErrorNPossErrorOKOKOK
ETMOSLARErrorNPossErrorOKOKOK
ETMOSSRRErrorNPossErrorunpOKunp
ETMDEVID, ETMAUTHSTATUSErrorNPossErrorOKOKOK
Other ManagementErrorNPossErrorOKOKOK
Reserved TraceErrorNPossErrorunpunpUNK/SBZP
Reserved ManagementErrorNPossErrorUNK/SBZPUNK/SBZPUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored.

[b] ETMLAR is not visible to coprocessor accesses, so writes are ignored.


Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211