3.12.2. Debugger accesses, ETMv3.5, SinglePower

Table 3.102 shows the behavior of debugger accesses in a SinglePower implementation in ETMv3.5. See ETM state definitions, ETMv3.5, SinglePower for the meanings of the column headings.

Table 3.102. Debugger accesses, ETMv3.5, SinglePower

 ETM state
RegisterNo PowerOtherwise
Trace registersErrorOK[a]
ETMLSRErrorOK/RAZ
ETMLAR[b]Errorunp
ETMPDCRErrorOK
ETMPDSRErrorOK
ETMOSLSRErrorOK
ETMOSLARErrorOK
ETMOSSRRErrorunp

ETMDEVID, ETMAUTHSTATUS

ErrorOK
ETMITCTRLErrorOK
Other ManagementErrorOK
Reserved TraceErrorUNK/SBZP
Reserved ManagementErrorUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored

[b] ETMLAR is not visible to Debugger accesses, so accesses are unpredictable.


Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211