3.12.3. Memory-mapped accesses, ETMv3.5, SinglePower

Table 3.103 shows the behavior of memory-mapped accesses in a SinglePower implementation in ETMv3.5. See ETM state definitions, ETMv3.5, SinglePower for the meanings of the column headings.

Table 3.103. Memory-mapped accesses, ETMv3.5, SinglePower

 ETM state
RegisterNo PowerOtherwise
Trace RegistersErrorOK[a][b]
ETMLSRErrorOK
ETMLARErrorOK
ETMPDCRErrorOK
ETMPDSRErrorOK
ETMOSLSRErrorOK
ETMOSLARErrorOK[b]
ETMOSSRRErrorunp
ETMDEVID, ETMAUTHSTATUSErrorOK
ETMITCTRLErrorOK[b]
Other ManagementErrorOK[b]
Reserved TraceErrorUNK/SBZP
Reserved ManagementErrorUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored

[b] When the CS Lock is set, these registers are WI.


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