3.13.2. Debugger accesses, ETMv3.5, multiple power domains

Table 3.105 shows debugger access permissions for multiple power implementations in ETM v3.5. See ETM state definitions, ETMv3.5, multiple power domains for the meanings of the column headings.

Table 3.105. Debugger accesses, ETMv3.5, multiple power domains

 ETM state   
RegisterNo Debug PowerNo Core PowerOS Lock setOtherwise
Trace registersErrorErrorErrorOK[a]
ETMLSRErrorOK/RAZOK/RAZOK/RAZ
ETMLAR[b]Errorunpunpunp
ETMPDCRErrorOKOKOK
ETMPDSRErrorOKOKOK
ETMOSLSRErrorOKOKOK
ETMOSLARErrorErrorOKOK
ETMOSSRRErrorunpunpunp
ETMDEVID, ETMAUTHSTATUSErrorOKOKOK
ETMITCTRLErrorimplementation definedimplementation definedOK
Other ManagementErrorOKOKOK
Reserved TraceErrorErrorErrorUNK/SBZP
Reserved ManagementErrorUNK/SBZPUNK/SBZPUNK/SBZP

[a] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored.

[b] ETMLAR is not visible to debugger accesses, so accesses are unpredictable.


Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211