3.13.3. Memory-mapped accesses, ETMv3.5, multiple power domains

Table 3.106 shows the behavior of memory-mapped ETM register accesses in an ETMv3.5 implementation that has separate debug and core power domains. See ETM state definitions, ETMv3.5, multiple power domains for the meanings of the column headings.

Table 3.106. Memory-mapped accesses, ETMv3.5, multiple power domains

 ETM state   

Register

No Debug PowerNo Core PowerOS Lock SetOtherwise
Trace registersErrorErrorOK[a][b]OK[b][c]
ETMLSRErrorOKOKOK
ETMLARErrorOKOKOK
ETMPDCRErrorOK[b]OK[b]OK[b]
ETMPDSRErrorOK[d]OK[d]OK[d]
ETMOSLSRErrorOKOKOK
ETMOSLARErrorErrorOK[b]OK[b]
ETMOSSRRErrorunpunpunp

ETMDEVID, ETMAUTHSTATUS

ErrorOK[b]OK[b]OK[b]
ETMITCTRLErrorimplementation definedimplementation definedOK[b]
Other ManagementErrorOK[b]OK[b]OK[b]
Reserved TraceErrorError

UNK/SBZP

UNK/SBZP

Reserved ManagementError

UNK/SBZP

UNK/SBZP

UNK/SBZP

[a] When the OS Lock is set, Trace registers must always be writeable regardless of the value of ETM_PD.

[b] When the CS Lock is set, these registers are WI.

[c] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored.

[d] When the CS Lock is set, reads from the ETMPDSR do not clear the Sticky State.


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