3.13.4. Coprocessor accesses, ETMv3.5, multiple power domains

Note

Coprocessor access to these registers is not possible when the core domain is powered down.

Table 3.107 shows coprocessor access permissions for multiple power implementations in ETM v3.5. See ETM state definitions, ETMv3.5, multiple power domains for the meanings of the column headings.

Table 3.107. Coprocessor accesses, ETMv3.5, multiple power domains

 ETM state   
RegisterNo Core PowerNon- PrivilegedOS Lock SetOtherwise[a]
Trace registersNPossErrorOK[b]OK[c]
ETMLSRNPossErrorunpunp
ETMLAR[d]NPossErrorunpunp
ETMPDSRNPossErrorunpunp
ETMOSLSRNPossErrorOKOK
ETMOSLARNPossErrorOKOK
ETMOSSRRNPossErrorunpunp
ETMDEVID, ETMAUTHSTATUSNPossErrorOKOK
ETMITCTRLNPossErrorunpunp
Other ManagementNPossErrorunpunp
Reserved TraceNPossErrorUNK/SBZPUNK/SBZP
Reserved ManagementNPossErrorunpunp

[a] These settings also apply to the No Debug Power state. This permits the ETM state to be saved and restored, and the ETM to be configured, when parts of the ETM are powered down.

[b] When the OS Lock is set, Trace registers must always be writeable regardless of the value of ETM_PD.

[c] When ETM_PD is 1, register writes to all Trace registers except certain bits of the ETMCR might be ignored.

[d] ETMLAR is not visible to coprocessor accesses, so writes are ignored.


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