4.9.1. Summary of ARM behavior

For a load or store, the mapping between the data address and data value in memory, and the value transferred to or from the register depends on:

The U bit controls whether certain unaligned loads and stores, such as LDR and STR, rotate the data value in the accessed word, or perform a true unaligned access (ARMv6 and later). This bit is set to 1 shortly after a processor reset and is normally left unchanged after this point. Therefore, its value is not included in the trace.

The B bit controls whether little-endian (LE) or word-invariant big-endian (BE-32) mappings apply to data transfers. In BE-32, byte and halfword transfers have their addresses modified so that the lowest addressed byte corresponds to the most significant byte of a word. For example, a load of a byte at address 0x2000 in fact loads the value at memory address 0x2003. This bit is set to 1 shortly after a processor reset and is normally left unchanged after this point. Therefore, its value is not included in the trace.

The E bit controls whether byte-invariant big-endian (BE-8, ARMv6 and later) mappings apply to data transfers. It cannot be set to 1 at the same time as the B bit. In BE-8, halfword and word transfers have the bytes in the data value swapped so that the most significant byte of a word is stored in the lowest addressed byte. Because this bit is in the CPSR, the setting of this bit can change between transfers. If it is set to 1, this is indicated in the trace with the data transfer if data address tracing is enabled.

If either the B or E bit is set to 1 during a VFP double-precision transfer, the word at the lower location corresponds to the high VFP register number, and the word at the higher location corresponds to the lower register number. For example, if a double-precision value is loaded from address 0x2000 into registers R0 and R1 in LE, the word at 0x2000 is loaded into register R0 and the word at 0x2004 is loaded into register R1. If however the transfer occurs in BE-8 or BE-32, the word at 0x2000 is loaded into register R1 and the word at 0x2004 is loaded into register R0.

For more information, see the ARM Architecture Reference Manual, where this topic is covered extensively.

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
Non-ConfidentialID101211