Embedded Trace Macrocell Architecture SpecificationETMv1.0 to ETMv3.5
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Embedded Trace Macrocell™ Architecture Specification

ETMv1.0 to ETMv3.5

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

Preface
About this specification
Product revision status
Intended audience
Using this specification
Conventions
Typographic conventions
Signals
Numbers
Additional reading
The ETM documentation suite
Other ARM publications
Feedback
Feedback on this specification
1. Introduction
1.1. About Embedded Trace Macrocells
1.1.1. Structure of an ETM
1.1.2. The debug environment
1.1.3. Thumb and Java support
1.1.4. Trace compression
1.2. ETM versions and variants
2. Controlling Tracing
2.1. About controlling tracing
2.2. ETM event resources
2.2.1. Memory access resources
2.2.2. Instrumentation resources, ETMv3.3 and later
2.2.3. Derived resources
2.2.4. External inputs
2.2.5. Example resource configuration
2.3. ETM event logic
2.4. Triggering a trace run
2.5. External outputs
2.6. Trace filtering
2.6.1. Definitions of when an ETM is tracing
2.6.2. Behavior while tracing is prohibited
2.6.3. Programming strategies
2.6.4. TraceEnable and filtering the instruction trace
2.6.5. ViewData and filtering the data trace
2.6.6. Preventing FIFO overflow
2.7. Address comparators
2.7.1. Comparator access size
2.7.2. Comparator access size field behavior, in ETMv3.1 and later
2.7.3. Comparator access size field behavior, in ETMv3.0 and earlier
2.7.4. Exact matching, in ETMv2.0 and later
2.7.5. Exact matching, in ETMv1.x
2.7.6. Behavior of address comparators
2.7.7. Access types for address range comparators
2.7.8. Comparator precision
2.7.9. Coprocessor transfers
2.7.10. Comparator configuration example
2.8. Operation of data value comparators
2.8.1. Terms used in this section
2.8.2. Operation of data value comparators, in ETMv3.2 and earlier
2.8.3. Operation of data value comparators, in ETMv3.3 and later
2.8.4. Summary of alignment and endianness considerations for different ETM versions
2.9. Instrumentation resources, from ETMv3.3
2.9.1. The Instrumentation resource event resources
2.9.2. Instructions for controlling the Instrumentation resources
2.9.3. Instrumentation resource behavior when tracing parallel execution
2.10. Trace port clocking modes
2.10.1. ETMv1 and ETMv2 behavior
2.10.2. ETMv3 behavior
2.11. Considerations for advanced processors, ETMv2 and later only
2.11.1. Parallel execution
2.11.2. Independent load/store unit
2.11.3. Consequences of parallel execution on counters
2.11.4. Consequences of parallel execution on the sequencer
2.12. Supported standard configurations in ETMv1
2.12.1. Choosing a configuration
2.12.2. ETM7 supported configurations
2.12.3. ETM9 supported configurations
2.13. Supported configurations from ETMv2
2.14. Behavior when non-invasive debug is disabled
3. Programmers’ Model
3.1. About the programmers’ model
3.2. Programming and reading ETM registers
3.2.1. Direct JTAG access
3.2.2. Coprocessor access, ETMv3.1 and later
3.2.3. Memory-mapped access, ETMv3.2 and later
3.2.4. Restrictions on the type of access to ETM registers
3.2.5. ETM register access models
3.2.6. Synchronization of ETM register updates
3.3. CoreSight support
3.3.1. Programmers’ model requirements
3.3.2. Topology detection requirements
3.4. The ETM registers
3.4.1. ETM Trace and ETM Management registers, from ETMv3.3
3.4.2. Reset behavior
3.4.3. Use of the Programming bit
3.4.4. ETM Programming bit and associated state
3.5. Detailed register descriptions
3.5.1. Main Control Register, ETMCR
3.5.2. Configuration Code Register, ETMCCR
3.5.3. Trigger Event Register, ETMTRIGGER
3.5.4. ASIC Control Register, ETMASICCR
3.5.5. ETM Status Register, ETMSR, ETMv1.1 and later
3.5.6. System Configuration Register, ETMSCR, ETMv1.2 and later
3.5.7. About the TraceEnable registers
3.5.8. TraceEnable Start/Stop Control Register, ETMTSSCR, ETMv1.2 and later
3.5.9. TraceEnable Control 2 Register, ETMTECR2, ETMv1.2 and later
3.5.10. TraceEnable Event Register, ETMTEEVR
3.5.11. TraceEnable Control 1 Register, ETMTECR1
3.5.12. Controlling FIFO overflow using the FIFOFULL registers
3.5.13. FIFOFULL Region Register, ETMFFRR
3.5.14. FIFOFULL Level Register, ETMFFLR
3.5.15. About the ViewData registers
3.5.16. ViewData Event Register, ETMVDEVR
3.5.17. ViewData Control 1 Register, ETMVDCR1
3.5.18. ViewData Control 2 Register, ETMVDCR2
3.5.19. ViewData Control 3 Register, ETMVDCR3
3.5.20. About the address comparator registers
3.5.21. Address Comparator Value Registers, ETMACVRn
3.5.22. Address Comparator Access Type Registers, ETMACTRn
3.5.23. About the data value comparator registers
3.5.24. Data Comparator Value Registers, ETMDCVRn
3.5.25. Data Comparator Mask Registers, ETMDCMRn
3.5.26. About the counter registers
3.5.27. Counter Reload Value Registers, ETMCNTRLDVRn
3.5.28. Counter Enable Registers, ETMCNTENRn
3.5.29. Counter Reload Event Registers, ETMCNTRLDEVRn
3.5.30. Counter Value Registers, ETMCNTVRn
3.5.31. About the sequencer registers
3.5.32. Sequencer State Transition Event Registers, ETMSQabEVR
3.5.33. Current Sequencer State Register, ETMSQR
3.5.34. External Output Event Registers, ETMEXTOUTEVRn
3.5.35. About the Context ID comparator registers, ETMv2.0 and later
3.5.36. Context ID Comparator Value Registers, ETMCIDCVRn
3.5.37. Context ID Comparator Mask Register, ETMCIDCMR
3.5.38. Implementation specific registers
3.5.39. Synchronization Frequency Register, ETMSYNCFR, ETMv2.0 and later
3.5.40. ID Register, ETMIDR, ETMv2.0 and later
3.5.41. Configuration Code Extension Register, ETMCCER, ETMv3.1 and later
3.5.42. Extended External Input Selection Register, ETMEXTINSELR, ETMv3.1 and later
3.5.43. TraceEnable Start/Stop EmbeddedICE Control Register, ETMTESSEICR, ETMv3.4
3.5.44. EmbeddedICE Behavior Control Register, ETMEIBCR, ETMv3.4 and later
3.5.45. Timestamp Event Register, ETMTSEVR, ETMv3.5
3.5.46. Auxiliary Control Register, ETMAUXCR, ETMv3.5
3.5.47. CoreSight Trace ID Register, ETMTRACEIDR, ETMv3.2 and later
3.5.48. VMID Comparator Value Register, ETMVMIDCVR, ETMv3.5
3.5.49. ETM ID Register 2, ETMIDR2, ETMv3.5
3.5.50. About the Operating System Save and Restore Registers, ETMv3.3 and later
3.5.51. OS Lock Access Register, ETMOSLAR, ETMv3.3 and later
3.5.52. OS Lock Status Register, ETMOSLSR, ETMv3.3 and later
3.5.53. OS Save and Restore Register, ETMOSSRR, ETMv3.3 and later
3.5.54. Device Power-Down Status Register, ETMPDSR, ETMv3.3 and later
3.5.55. Power Down Control Register, ETMPDCR, ETMv3.5
3.5.56. Integration Mode Control Register, ETMITCTRL, ETMv3.2 and later
3.5.57. About the claim tag registers, ETMv3.2 and later
3.5.58. Claim Tag Set Register, ETMCLAIMSET
3.5.59. Claim Tag Clear Register, ETMCLAIMCLR
3.5.60. About the lock registers, ETMv3.2 and later
3.5.61. Lock Access Register, ETMLAR, ETMv3.2 and later
3.5.62. Lock Status Register, ETMLSR, ETMv3.2 and later
3.5.63. Authentication Status Register, ETMAUTHSTATUS, ETMv3.2 and later
3.5.64. CoreSight Device Configuration Register, ETMDEVID, ETMv3.2 and later
3.5.65. CoreSight Device Type Register, ETMDEVTYPE, ETMv3.2 and later
3.5.66. About the CoreSight Peripheral Identification Registers, ETMv3.2 and later
3.5.67. Peripheral ID0 Register, ETMPIDR0
3.5.68. Peripheral ID1 Register, ETMPIDR1
3.5.69. Peripheral ID2 Register, ETMPIDR2
3.5.70. Peripheral ID3 Register, ETMPIDR3
3.5.71. Peripheral ID4 Register, ETMPIDR4
3.5.72. Peripheral ID5 to Peripheral ID7 Registers, ETMPIDR5 to ETMPIDR7
3.5.73. About the CoreSight component identification registers, ETMv3.2 and later
3.5.74. Component ID0 Register, ETMCIDR0
3.5.75. Component ID1 Register, ETMCIDR1
3.5.76. Component ID2 Register, ETMCIDR2
3.5.77. Component ID3 Register, ETMCIDR3
3.6. Using ETM event resources
3.6.1. Resource identification
3.6.2. Boolean combinations for defining events
3.6.3. Examples of event and resource programming
3.7. Example ViewData and TraceEnable configurations
3.7.1. An example ViewData configuration
3.7.2. An example TraceEnable configuration
3.8. Power Down support
3.8.1. Power down support in ETMv3.3 and ETMv3.4
3.8.2. Power down support in ETMv3.5
3.8.3. ETM behavior when the OS Lock is set
3.8.4. Guidelines for the ETM trace registers to be saved and restored
3.9. About the access permissions for ETM registers
3.9.1. Access types
3.9.2. Meanings of terms and abbreviations used in this section
3.9.3. Restrictions on accesses using a Direct JTAG connection
3.9.4. Effect of DBGSWENABLE on register access
3.10. Access permissions for ETMv3.3 and ETMv3.4, SinglePower
3.10.1. ETM state definitions, ETMv3.3 and ETMv3.4, SinglePower
3.10.2. Debugger accesses, ETMv3.3 and ETMv3.4, SinglePower
3.10.3. Memory-mapped accesses, ETMv3.3 and ETMv3.4, SinglePower
3.10.4. Coprocessor accesses, ETMv3.3 and ETMv3.4, SinglePower
3.11. Access permissions for ETMv3.3 and ETMv3.4, multiple power domains
3.11.1. ETM state definitions, ETMv3.3 and ETMv3.4, multiple power domains
3.11.2. Debugger accesses, ETMv3.3 and ETMv3.4, multiple power domains
3.11.3. Memory-mapped accesses, ETMv3.3 and ETMv3.4, multiple power domains
3.11.4. Coprocessor accesses, ETMv3.3 and ETMv3.4, multiple power domains
3.12. Access permissions for ETMv3.5, SinglePower
3.12.1. ETM state definitions, ETMv3.5, SinglePower
3.12.2. Debugger accesses, ETMv3.5, SinglePower
3.12.3. Memory-mapped accesses, ETMv3.5, SinglePower
3.12.4. Coprocessor accesses, ETMv3.5, SinglePower
3.13. Access permissions for ETMv3.5, multiple power domains
3.13.1. ETM state definitions, ETMv3.5, multiple power domains
3.13.2. Debugger accesses, ETMv3.5, multiple power domains
3.13.3. Memory-mapped accesses, ETMv3.5, multiple power domains
3.13.4. Coprocessor accesses, ETMv3.5, multiple power domains
4. Signal Protocol Overview
4.1. About trace information
4.2. Signal protocol variants
4.3. Structure of the trace port
4.3.1. Signals
4.3.2. Multiplexed trace port (ETMv1.x and ETMv2.x only)
4.3.3. Demultiplexed trace port (ETMv1.x and ETMv2.x only)
4.3.4. ETM structures
4.4. Decoding required by trace capture devices
4.4.1. Trigger conditions
4.4.2. Trace disabled conditions
4.5. Instruction trace
4.5.1. Instruction trace filtering
4.5.2. Direct and indirect branches
4.5.3. Exceptions
4.5.4. 32-bit Thumb instructions
4.5.5. Thumb CBZ and CBNZ instructions
4.6. Data trace
4.6.1. Data access filtering
4.6.2. Address and data selection
4.6.3. Preloads
4.6.4. Asynchronous data aborts
4.7. Context ID tracing
4.8. Debug state
4.9. Endian effects and unaligned access
4.9.1. Summary of ARM behavior
4.9.2. Representation of data in the trace
4.10. Definitions
4.10.1. Load/Store Multiple (LSM) instructions
4.10.2. Data Instructions
4.10.3. Direct branch instructions
4.10.4. Exception return instructions
4.11. Coprocessor operations
4.11.1. Coprocessor data operation
4.11.2. Coprocessor data transfer
4.11.3. Coprocessor register transfer
4.12. Wait For Interrupt and Wait For Event
5. ETMv1 Signal Protocol
5.1. ETMv1 pipeline status signals
5.1.1. Trigger PIPESTAT signals
5.2. ETMv1 trace packets
5.3. Rules for generating and analyzing the trace in ETMv1
5.3.1. Additional considerations for 16-bit ports
5.3.2. Example ETMv1 trace
5.4. Pipeline status and trace packet association in ETMv1
5.5. Instruction tracing in ETMv1
5.5.1. Direct branches to the exception vector table
5.5.2. ARM and Thumb code
5.5.3. Java code
5.5.4. Compressed branch address packet structure
5.5.5. Branch reason codes
5.6. Trace synchronization in ETMv1
5.6.1. Address Packet Offset
5.6.2. Full address output
5.6.3. Context ID tracing
5.7. Data tracing in ETMv1
5.7.1. PIPESTAT signals indicating data accesses in the pipeline
5.7.2. Load/Store Multiple instructions
5.7.3. Trace packet sequence for data accesses
5.7.4. Data aborts
5.7.5. Address compression performed by the ETM
5.8. Filtering the ETMv1 trace
5.8.1. Enabling trace
5.8.2. Disabling trace
5.8.3. Data accesses during disabled trace
5.8.4. Precise events
5.9. FIFO overflow
5.9.1. System stalling
5.10. Cycle-accurate tracing
5.11. Tracing Java code, ETMv1.3 only
6. ETMv2 Signal Protocol
6.1. ETMv2 pipeline status signals
6.1.1. Wait PIPESTAT signals
6.1.2. Branch phantom PIPESTAT signals
6.1.3. Data PIPESTAT signals
6.1.4. Instruction Executed PIPESTAT signals
6.1.5. Instruction Not Executed PIPESTAT signals
6.1.6. TD PIPESTAT signals
6.1.7. Trigger PIPESTAT signals
6.2. ETMv2 trace packets
6.3. Rules for generating and analyzing the trace in ETMv2
6.4. Trace packet types
6.4.1. Trace packet headers
6.4.2. Normal Data packets
6.4.3. Load Miss packets
6.4.4. Value Not Traced packets
6.4.5. Context ID packets
6.5. Trace synchronization in ETMv2
6.5.1. Trace FIFO offsets
6.5.2. TFO packet types
6.5.3. TFO packet headers
6.5.4. Normal TFO packets
6.5.5. LSM In Progress TFO packets
6.5.6. Data address synchronization
6.5.7. Context ID tracing
6.6. Tracing through regions with no code image
6.7. Instruction tracing with ETMv2
6.7.1. Branch Address trace packets
6.7.2. Full branch address reason codes
6.8. Data tracing in ETMv2
6.8.1. Data aborts
6.8.2. Decoding the data trace packets
6.8.3. Address compression performed by the ETM
6.9. Filtering the ETMv2 trace
6.9.1. Enabling trace
6.9.2. Disabling trace
6.9.3. Data accesses during disabled trace
6.10. FIFO overflow
6.11. Cycle-accurate tracing
7. ETMv3 Signal Protocol
7.1. Introduction
7.2. Packet types
7.3. Instruction tracing
7.3.1. P-headers
7.3.2. Condition codes on canceled and undefined instructions
7.3.3. Cycle information, for cycle-accurate tracing
7.3.4. Cycle count packet
7.3.5. Branch Packets
7.3.6. Context ID packets
7.3.7. VMID packets, ETMv3.5
7.3.8. Exceptions when leaving Debug state
7.4. Data tracing
7.4.1. Data packet types
7.4.2. Normal data packet
7.4.3. Out-of-order packets
7.4.4. Tracing LSMs
7.4.5. Value not traced packet
7.4.6. Data suppressed packet
7.4.7. Store failed packet
7.4.8. Jazelle data tracing
7.4.9. Data aborts
7.4.10. Data-only mode, ETMv3.1 and later
7.4.11. Data tracing options, ETMv3.3 and later
7.4.12. Exceptions on Data Instructions
7.5. Additional trace features for ARMv7‑M processors, from ETMv3.4
7.5.1. Support for a large number of exceptions
7.5.2. Instructions that can be paused for continuation
7.5.3. Automatic stack push on exception entry and pop on exception exit
7.5.4. Tracing return from an exception
7.6. Tracing of exception return, ETMv3.5
7.6.1. Cancelling an exception return
7.7. Timestamping, ETMv3.5
7.7.1. Rules for generating timestamps
7.7.2. Cycle accuracy
7.7.3. Encoding of the timestamp value
7.7.4. Timestamp packet
7.8. Virtualization Extensions, ETMv3.5
7.9. Behavior of EmbeddedICE inputs, from ETMv3.4
7.9.1. EmbeddedICE watchpoint comparator input behavior
7.9.2. Default behavior of EmbeddedICE watchpoint inputs
7.9.3. Implementation of pulse and latch behavior of EmbeddedICE inputs
7.9.4. EmbeddedICE input usage examples
7.10. Synchronization
7.10.1. Frequency of synchronization
7.10.2. NonPeriodic synchronization
7.10.3. Periodic synchronization
7.10.4. A-sync, alignment synchronization
7.10.5. I-sync instruction synchronization
7.10.6. D-sync, data address synchronization
7.11. Trace port interface
7.11.1. Trigger
7.11.2. Ignore
7.11.3. FIFO draining
7.12. Tracing through regions with no code image
7.13. Cycle-accurate tracing
7.13.1. Tracing long gaps in cycle-accurate trace
7.13.2. Support for cycle-accurate tracing, ETMv3.3 and later
7.14. ETMv2 and ETMv3 compared
7.14.1. ETMv2 PIPESTAT encodings and ETMv3 P-headers compared
7.14.2. ETMv2 TFO packets and ETMv3 I-sync packets compared
8. Trace Port Physical Interface
8.1. Target system connector
8.2. Target connector pinouts
8.2.1. Assignment of trace information pins between ETM architecture versions
8.2.2. Single target connector pinout
8.2.3. Dual target connector pinout
8.2.4. Multiplexed trace port, single target connector pinout (ETMv1.x and ETMv2.x)
8.2.5. Demultiplexed trace port target connector pinout
8.2.6. Signal descriptions
8.3. Connector placement
8.3.1. Connector orientation
8.3.2. Dual connector placement
8.4. Timing specifications
8.4.1. Half-rate clocking mode
8.5. Signal level specifications
8.6. Other target requirements
8.7. JTAG control connector
9. Tracing Dynamically Loaded Images
9.1. About tracing dynamically-loaded code
9.1.1. Simple overlay support
9.2. Software support for Context ID
9.3. Hardware support for Context ID
A. ETM Quick Reference Information
A.1. ETM event resources
A.1.1. Resource identification and event encoding
A.1.2. Resource control registers
A.2. Summary of implementation defined ETM features
B. Architecture Version Information
B.1. ETMv1
B.1.1. ETMv1.0 to ETMv1.1
B.1.2. ETMv1.1 to ETMv1.2
B.1.3. ETMv1.2 to ETMv1.3
B.2. ETMv2
B.2.1. ETMv1.3 to ETMv2.0
B.2.2. ETMv2.0 to ETMv2.1
B.3. ETMv3
B.3.1. ETMv2.1 to ETMv3.0
B.3.2. ETMv3.0 to ETMv3.1
B.3.3. ETMv3.1 to ETMv3.2
B.3.4. ETMv3.2 to ETMv3.3
B.3.5. ETMv3.3 to ETMv3.4
B.3.6. ETMv3.4 to ETMv3.5
Glossary

List of Figures

1.1. Example debugging environment with TPA
1.2. Example debugging environment with ETB
2.1. Sequencer state diagram
2.2. Extended external inputs example
2.3. Example resource configuration
2.4. Address comparator match filtering in ETMv3.5
2.5. TraceEnable configuration
2.6. Programming the TraceEnable logic
2.7. Trace start/stop block
2.8. ViewData configuration
2.9. Programming the ViewData logic
2.10. FIFOFULL generation
2.11. Programming the FIFOFULL logic
2.12. SuppressData inputs
2.13. Programming the data suppression logic
2.14. Single address comparisons in ETMv3.1 and later
2.15. Range comparisons in ETMv3.1 and later
2.16. Successful match of a byte access with word mask set
2.17. Successful match of word access with word mask set
2.18. Successful match of byte access on byte watch with word mask set
2.19. Unwanted match of byte access on byte watch with word mask set
2.20. Failed match with no mask
2.21. Range address successful match, in ETMv3.0 or earlier
2.22. Range address failed match, in ETMv3.0 or earlier
3.1. ETM JTAG structure
3.2. Mapping from register number to CP14 instruction fields
3.3. Programming ETM registers
3.4. ETMCR bit assignments
3.5. ETMCCR bit assignments, from architecture v3.1
3.6. ETMCCR bit assignments for architecture v1.x
3.7. ETMTRIGGER register bit assignments
3.8. ETMASICCR bit assignments
3.9. ETMSR bit assignments for architecture v3.1
3.10. ETMSCR bit assignments for architecture v3.2
3.11. ETMTSSCR bit assignments
3.12. ETMTECR2 bit assignments
3.13. ETMTEEVR bit assignments
3.14. ETMTECR1 bit assignments
3.15. ETMFFRR bit assignments
3.16. ETMFFLR bit assignments
3.17. ETMVDEVR bit assignments
3.18. ETMVDCR1 bit assignments
3.19. ETMVDCR2 bit assignments
3.20. ETMVDCR3 bit assignments
3.21. ETMACVR bit assignments
3.22. ETMACTR bit assignments in ETMv3.5
3.23. ETMACTR bit assignments for ETMv3.4
3.24. ETMDCVR bit assignments
3.25. ETMDCMR bit assignments
3.26. ETMCNTRLDVR bit assignments
3.27. ETMCNTENR bit assignments
3.28. ETMCNTRLDEVR bit assignments
3.29. ETMCNTVR bit assignments
3.30. ETMSQabEVR bit assignments
3.31. ETMSQR bit assignments
3.32. ETMEXTOUTEVR bit assignments
3.33. ETMCIDCVR bit assignments
3.34. ETMCIDCMR bit assignments
3.35. implementation specific Register 0 bit assignments
3.36. ETMSYNCFR bit assignments
3.37. ETMIDR bit assignments, for ETM architecture v3.4
3.38. ETMCCER bit assignments
3.39. ETMEXTINSELR bit assignments
3.40. ETMTESSEICR bit assignments
3.41. ETMEIBCR bit assignments
3.42. ETMTSEVR bit assignments
3.43. ETMTRACEIDR bit assignments
3.44. ETMVMIDCVR bit assignments
3.45. ETMIDR2 bit assignments
3.46. ETMOSLAR bit assignments
3.47. ETMOSLSR bit assignments
3.48. ETMOSSRR bit assignments
3.49. ETMPDSR bit assignments
3.50. ETMPDCR register bit assignments
3.51. ETMITCTRL register bit assignments
3.52. ETMCLAIMSET register bit assignments
3.53. ETMCLAIMCLR register bit assignments
3.54. ETMLAR bit assignments
3.55. ETMLSR bit assignments
3.56. ETMAUTHSTATUS register bit assignments
3.57. Secure non-invasive debug enable logic when controlled by the ETM
3.58. ETMDEVID register bit assignments
3.59. ETMDEVTYPE register bit assignments
3.60. Mapping between the Peripheral ID Registers and the Peripheral ID value
3.61. Peripheral ID fields
3.62. ETMPIDR0 bit assignments
3.63. ETMPIDR1 bit assignments
3.64. ETMPIDR2 bit assignments
3.65. ETMPIDR3 bit assignments
3.66. ETMPIDR4 bit assignments
3.67. ETMPIDR5 to ETMPIDR7 bit assignments
3.68. Mapping between the Component ID registers and the Component ID value
3.69. ETMCIDR0 bit assignments
3.70. ETMCIDR1 bit assignments
3.71. ETMCIDR2 bit assignments
3.72. ETMCIDR3 bit assignments
3.73. Event and resource encoding
3.74. Example ViewData configuration
3.75. ETMVDEVR example
3.76. ETMVDCR1 example
3.77. ETMVDCR3 example
3.78. Example ViewData composite range
3.79. Example TraceEnable configuration
3.80. ETMTEEVR example
3.81. ETMTECR1 example
3.82. ETMTSSCR example
4.1. ETMv1.x structure
4.2. ETMv2.x structure
4.3. ETMv3.x structure
5.1. Full address output in ARM and Thumb state
6.1. Generating an ARM branch address
6.2. Generating a Thumb branch address
6.3. Full branch address encodings for ARM and Thumb states
7.1. Cycle count packet
7.2. Branch packet structure
7.3. Original encoding of ARM state branch address bytes
7.4. Original encoding of Thumb state branch address bytes
7.5. Original encoding of Jazelle state branch address bytes
7.6. Original encoding of ARM state branch with exception address bytes
7.7. Normal Thumb branch with no change in address bits [31:7]
7.8. Normal Thumb branch with no change in address bits [31:14]
7.9. Normal Thumb branch with no change in address bits [31:21]
7.10. Normal Thumb branch with no change in address bits [31:28]
7.11. Normal Thumb branch with a change in address bits [31:28]
7.12. Alternative encoding of normal Thumb branch with no change in address bits [31:7]
7.13. Alternative encoding of normal Thumb branch with no change in address bits [31:13]
7.14. Alternative encoding of normal Thumb branch with no change in address bits [31:20]
7.15. Alternative encoding of normal Thumb branch with no change in address bits [31:27]
7.16. Alternative encoding of normal Thumb branch when address bits [31:27] change
7.17. Alternative encoding of normal ARM branch with no change in address bits [31:14]
7.18. Alternative encoding of normal Jazelle branch with no change in address bits [31:19]
7.19. Thumb branch with exception information bytes and no change in address bits [31:13], alternative encoding
7.20. Thumb branch with exception information bytes and no change in address bits [31:20], alternative encoding
7.21. Thumb branch with exception information bytes and no change in address bits [31:27], alternative encoding
7.22. Thumb branch with exception information bytes and when address bits [31:27] change, alternative encoding
7.23. ARM branch with exception information bytes and no change in address bits [31:21], alternative encoding
7.24. Jazelle branch with exception information bytes and no change in address bits [31:26], alternative encoding
7.25. Format of Exception Information Bytes
7.26. Only Exception information byte 0 is output
7.27. Only Exception information bytes 0 and 1 are output
7.28. Only Exception information bytes 0 and 2 are output
7.29. All Exception information bytes are output
7.30. Context ID packet
7.31. VMID packet
7.32. Normal data packet for ETMv3.0 and later
7.33. Out-of-order placeholder packet
7.34. Out-of-order data packet for ETMv3.0 and later
7.35. Value not traced packet
7.36. Data suppressed packet
7.37. Store failed packet
7.38. Exception entry packet, ETMv3.4 and later
7.39. Return from exception packet, ETMv3.4 and later
7.40. 48-bit timestamp packet
7.41. 64-bit timestamp packet
7.42. Normal I-sync packet
7.43. Normal I-sync with cycle count packet
7.44. LSiP I-sync packet
7.45. LSiP I-sync with cycle count packet
7.46. Data-only I-sync packet
7.47. Trigger packet
7.48. Ignore packet
8.1. Recommended connector orientation
8.2. Recommended dual connector orientation
8.3. TRACECLK specification
8.4. Trace data specification
9.1. SDRAM overlay examples
9.2. Memory map and overlay physical address space
A.1. Writing to an Event Register

List of Tables

1.1. ETM versions and variants
2.1. Filter CPRT and monitor CPRT combinations
2.2. Effect of exact match bit settings for instruction address comparisons
2.3. Data value comparisons for normal transfers
2.4. Data value comparisons on an out-of-order transfer
2.5. Context-dependent behavior of single address comparators
2.6. Context-dependent behavior of address range comparators, from ETMv3.3
2.7. Context-dependent behavior of address range comparators, before ETMv3.3
2.8. Single address and address range comparators example
2.9. Alignment considerations in ETMv1.x
2.10. Alignment considerations in ETMv2.0 to ETMv3.2
2.11. Alignment considerations in ETMv3.3 and later
2.12. The instrumentation resource event resources
2.13. Hint field encodings for the instrumentation instructions
2.14. Instrumentation resource parallel execution examples for two instructions
2.15. Clocking, port mode, port speed, and data pins in ETMv1 and ETMv2
2.16. Port mode, port speed and data pins in ETMv3
2.17. ETM7 configurations
2.18. ETM9 configurations
3.1. Typical ETM register access implementations
3.2. ETM logical interfaces
3.3. ETM register summary
3.4. Split of ETM register map into Trace and Management registers
3.5. ETMCR bit assignments
3.6. ETM port size
3.7. ETMCR checks for implementation defined features
3.8. Testing whether data suppression is supported, in ETMv3.3 and later
3.9. Permitted Suppress data and Stall processor settings, ETMCR
3.10. Testing whether cycle-accurate tracing is supported, ETMv3.3 and later
3.11. Testing which data tracing features are implemented, ETMv3.3 and later
3.12. ETMCCR bit assignments
3.13. ETMTRIGGER register bit assignments
3.14. ETMASICCR bit assignments
3.15. ETMSR bit assignments
3.16. ETMSCR bit assignments
3.17. ETMTSSCR bit assignments
3.18. ETMTECR2 bit assignments
3.19. ETMTEEVR bit assignments
3.20. ETMTECR1 bit assignments
3.21. ETMFFRR bit assignments
3.22. ETMFFLR bit assignments
3.23. Supported FIFOFULL and data suppression modes in ETMv3.0 and later
3.24. ETMVDEVR bit assignments
3.25. ETMVDCR1 bit assignments
3.26. ETMVDCR2 bit assignments
3.27. ETMVDCR3 bit assignments
3.28. ETMACVR bit assignments
3.29. ETMACTR bit assignments
3.30. Address comparator filtering by state and mode, ETMv3.5 with Security Extensions
3.31. Address comparator filtering by state and mode, ETMv3.5, no Security Extensions
3.32. Summary of the data value comparator registers
3.33. Example comparator register associations for a medium-sized configuration
3.34. ETMDCVR bit assignments
3.35. ETMDCMR bit assignments
3.36. Summary of counter registers
3.37. ETMCNTRLDVR bit assignments
3.38. ETMCNTENR bit assignments
3.39. ETMCNTRLDEVR bit assignments
3.40. ETMCNTVR bit assignments
3.41. Sequencer register allocation
3.42. ETMSQabEVR bit assignments
3.43. ETMSQR bit assignments
3.44. ETMEXTOUTEVR bit assignments
3.45. Context ID comparator registers
3.46. ETMCIDCVR bit assignments
3.47. ETMCIDCMR bit assignments
3.48. implementation specific Register 0 default bit assignments
3.49. ETMSYNCFR bit assignments
3.50. ETMIDR bit assignments
3.51. ID values for different ETM variants
3.52. ETMCCER bit assignments
3.53. ETMEXTINSELR bit assignments
3.54. ETMTESSEICR bit assignments
3.55. ETMEIBCR bit assignments
3.56. ETMTSEVR bit assignments
3.57. ETMTRACEIDR bit assignments
3.58. ETMVMIDCVR bit assignments
3.59. ETMIDR2 bit assignments
3.60. ETMOSLAR bit assignments
3.61. ETMOSLSR bit assignments
3.62. ETMOSSRR bit assignments
3.63. ETMPDSR bit assignments
3.64. ETMPDSR encodings
3.65. ETMPDCR register bit assignments
3.66. ETMITCTRL register bit assignments
3.67. ETMCLAIMSET register bit assignments
3.68. ETMCLAIMCLR register bit assignments
3.69. ETMLAR bit assignments
3.70. ETMLSR bit assignments
3.71. ETMAUTHSTATUS register bit assignments
3.72. Implementation of the Secure non-invasive debug field
3.73. ETMDEVID register bit assignments
3.74. ETMDEVTYPE register bit assignments
3.75. Summary of the Peripheral Identification Registers
3.76. Register fields for the Peripheral Identification Registers
3.77. ETMPIDR0 bit assignments
3.78. ETMPIDR1 bit assignments
3.79. ETMPIDR2 bit assignments
3.80. ETMPIDR3 bit assignments
3.81. ETMPIDR4 bit assignments
3.82. ETMPIDR5 to ETMPIDR7 bit assignments
3.83. Summary of the CoreSight component Identification registers
3.84. ETMCIDR0 bit assignments
3.85. ETMCIDR1 bit assignments
3.86. ETMCIDR2 bit assignments
3.87. ETMCIDR3 bit assignments
3.88. Resource encodings
3.89. Resource identification encoding
3.90. Boolean function encoding for events
3.91. Event encoding
3.92. Example comparator inputs
3.93. ETMTECR1 example values
3.94. Determining the level of power down support
3.95. Typical list of ETM registers to be saved and restored
3.96. Debugger accesses, ETMv3.3 and ETMv3.4, SinglePower
3.97. Memory-mapped accesses, ETMv3.3 and ETMv3.4, SinglePower
3.98. Coprocessor accesses, ETMv3.3 and ETMv3.4, SinglePower
3.99. Debugger accesses, ETMv3.3 and ETMv3.4, multiple power domains
3.100. Memory-mapped accesses. ETMv3.3 and ETMv3.4, multiple power domains
3.101. Coprocessor accesses. ETMv3.3 and ETMv3.4, multiple power domains
3.102. Debugger accesses, ETMv3.5, SinglePower
3.103. Memory-mapped accesses, ETMv3.5, SinglePower
3.104. Coprocessor accesses, ETMv3.5, SinglePower
3.105. Debugger accesses, ETMv3.5, multiple power domains
3.106. Memory-mapped accesses, ETMv3.5, multiple power domains
3.107. Coprocessor accesses, ETMv3.5, multiple power domains
4.1. Trace disabled conditions
4.2. ETMv3 exception tracing
4.3. ETMCR ProcIDSize bits
4.4. Exception return instructions
5.1. PIPESTAT messages
5.2. PIPESTAT and TRACEPKT association
5.3. Branch reason codes
6.1. PIPESTAT messages
6.2. Trace packet header encodings
6.3. SS bit encodings
6.4. TFO encodings
6.5. Example signal sequence for a mid-byte TFO
6.6. TFO packet header encodings
6.7. TFO reason codes
6.8. Comparison of Normal and LSM in progress TFO packets
6.9. ARM and Thumb 5-byte addresses
7.1. Header encodings
7.2. P-header encodings in non cycle-accurate mode
7.3. Cycle count and P-header encodings in cycle-accurate mode
7.4. Use of format 4 P-header in cycle-accurate mode
7.5. Interpretation of missing fields in branch packets
7.6. Address Byte 5 encodings, original encoding scheme
7.7. EEE field encodings, original branch encoding scheme
7.8. Interpretation of bits [7:6] in Address bytes 1-4
7.9. Meanings of fields in Exception Information Bytes
7.10. Requirements for Exception Information Bytes
7.11. Encoding of Exception[8:0] for ARMv7-M processors
7.12. Encoding of Exception[3:0] for non-ARMv7-M processors
7.13. Meaning of the AltISA bit in the Continuation byte
7.14. State change branch packets
7.15. Direct branch with change from ARM to Thumb state
7.16. Direct branch with changes between Thumb and ThumbEE states
7.17. Size bit encoding combinations
7.18. Possible feature sets for data tracing, ETMv3.3 and later
7.19. Default behavior of EmbeddedICE watchpoint comparator inputs
7.20. Processor state information in I-sync packets, ETMv3.3 and later
7.21. ETMv3 reason codes
7.22. Mappings from pipeline status to P-header atoms
8.1. Connector part numbers
8.2. Trace signal names
8.3. Single target connector pinout
8.4. Pipeline status seen by old TPAs
8.5. Second target connector pinout ETMv3.x
8.6. Dual target connector pinout
8.7. Multiplexed trace port, single target connector pinout
8.8. Paired signals in a multiplexed trace port connector
8.9. Demultiplexed 4-bit connector pinout
8.10. TRACECLK timing requirements
8.11. Rise and fall time requirements
8.12. Trace port setup and hold requirements
A.1. Resource identification encoding
A.2. Boolean function encoding for events
A.3. Locations of ETM event registers
A.4. ETMASICCR, register 0x003
A.5. ETMTSSCR, register 0x006
A.6. ETMTECR1, register 0x009
A.7. ETMTECR2, register 0x007
A.8. ETMFFRR, register 0x00A
A.9. ETMFFLR, register 0x00B
A.10. ETMVDCR1, register 0x00D
A.11. ETMVDCR2, register 0x00E
A.12. ETMVDCR3, register 0x00F
A.13. ETMACVRs, registers 0x010-0x01F
A.14. ETMACTRs, registers 0x020-0x02F
A.15. Exact match bit settings for instruction accesses
A.16. Exact match bit settings for data accesses
A.17. ETMDCVRs, registers 0x030-0x03F
A.18. ETMDCMRs, registers 0x040-0x04F
A.19. ETMCNTRLDVRs, registers 0x050-0x053
A.20. ETMCNTENRs, registers 0x054-0x057
A.21. ETMCNTVRs, registers 0x05C-0x05F
A.22. ETMSQR, register 0x067
A.23. ETMEXTOUTEVRs, registers 0x068-0x06B
A.24. Locations of the ETMCIDCVRs
A.25. ETMCIDCVRs, registers 0x06C-0x06E
A.26. ETMCIDCMR, register 0x06F
A.27. ETMSYNCFR, register 0x078
A.28. ETMEXTINSELR, register 0x07B
A.29. ETMv3.4 features with implementation defined number of instances or size
A.30. Optional features in ETMv3.4

Proprietary Notice

This Embedded Trace Macrocell Architecture Specification is protected by copyright and the practice or implementation of the information herein may be protected by one or more patents or pending applications. No part of this Embedded Trace Macrocell Architecture Specification may be reproduced in any form by any means without the express prior written permission of ARM. No license, express or implied, by estoppel or otherwise to any intellectual property rights is granted by this Embedded Trace Macrocell Architecture Specification.

Your access to the information in this Embedded Trace Macrocell Architecture Specification is conditional upon your acceptance that you will not use or permit others to use the information for the purposes of determining whether implementations of the ARM architecture infringe any third party patents.

This Embedded Trace Macrocell Architecture Specification is provided “as is”. ARM makes no representations or warranties, either express or implied, included but not limited to, warranties of merchantability, fitness for a particular purpose, or non-infringement, that the content of this Embedded Trace Macrocell Architecture Specification is suitable for any particular purpose or that any practice or implementation of the contents of the Embedded Trace Macrocell Architecture Specification will not infringe any third party patents, copyrights, trade secrets, or other rights.

This Embedded Trace Macrocell Architecture Specification may include technical inaccuracies or typographical errors.

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Words and logos marked with ® or TM are registered trademarks or trademarks of ARM Limited, except as otherwise stated below in this proprietary notice. Other brands and names mentioned herein may be the trademarks of their respective owners.

Copyright © 1999-2002, 2004-2009, 2011 ARM Limited

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In this document, where the term ARM is used to refer to the company it means “ARM or any of its subsidiaries as appropriate”.

Note

The term ARM is also used to refer to versions of the ARM architecture, for example ARMv6 refers to version 6 of the ARM architecture. The context makes it clear when the term is used in this way.

Revision History
Revision A30 March 1999First release for ETMv1.0 and ETMv1.1.
Revision B12 July 1999Errata 01 corrections incorporated for ETMv1.1 and ETMv1.0.
Revision C03 December 1999Protocol enhancements and modified trace port connector pinout added. ETMv1.0 and ETMv1.1 release.
Revision D18 May 2000Protocol version 2 enhancements added. ETMv1.2 release.
Revision E06 September 2000Minor corrections to Issue D incorporated. ETMv1.2 release.
Revision F15 January 2001Protocol version 3 enhancements added to support the tracing of Java instructions. ETMv1.3 release.
Revision G08 May 2001Description of protocol versions and variants included. Released in conjunction with fixes to errata in ETMv1.2 and ETMv1.3.
Revision H25 July 2001Description of ETMv2.0 enhancements included.
Revision I17 December 2002Incorporation of ETMv2.1, ETMv3.0, and ETMv3.1 architectures.
Revision J16 July 2004Incorporation of ETMv3.2 architecture.
Revision K17 March 2005Minor corrections and updates.
Revision L04 November 2005Incorporates ETMv3.3 architecture, re-organizes descriptions of address comparators, and has minor enhancements elsewhere.
Revision M14 December 2005Final draft of ETMv3.4 issue.
Revision N08 February 2006Non-confidential release of ETMv3.4 issue. No change to content.
Revision O20 July 2007Various enhancements, updates and corrections, incorporating all errata to Issue N. Updated Implementer codes list. Added summary of implementation defined ETM features to Appendix A.
Revision P18 December 2009First release for ETMv3.5.
Revision Q23 September 2011Minor corrections and updates.
Copyright © 1999-2002, 2004-2009, 2011 ARM Limited. All rights reserved.ARM IHI 0014Q
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