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The following tables list the ARMv7 instructions that are always classified as waypoint instructions:
Unpredictable encodings describes the PFT requirements when the processor attempts to execute an instruction encoding that the architecture defines as unpredictable.
Table 2.2. Direct branches, ARM instruction set
| Instruction | Description |
|---|---|
B | Unconditional branch |
B<cc> | Conditional Branch |
BL | Branch and Link |
BLX <immed> | Branch with link and exchange |
ISB | Instruction Synchronization Barrier (ISB), including CP15 encodings [1] |
DMB | Data Memory Barrier (DMB), including CP15 encodings [1], if supported[2] |
DSB | Data Synchronization Barrier (DSB), including CP15 encodings [1], if supported [2] |
[1] Includes the CP15 encodings in ARMv7 and in earlier versions of the ARM architecture. [2] Bit [24] of the ETMCCER determines whether the PTM treats DMB and DSB operations as waypoint instructions, see Configuration Code Extension Register, ETMCCER. | |
Table 2.3. Direct branches, Thumb and ThumbEE instruction sets
| Instruction | Description | |
|---|---|---|
| 16-bit instruction space | ||
B | Unconditional branch | |
B<cc> | Conditional Branch | |
CZB or CNZB | Compare with zero and branch | |
| 32-bit instruction space | ||
B | Unconditional branch | |
B<cc> | Conditional Branch | |
BL <immed> | Branch and Link | |
BLX <immed> | Branch with link and exchange | |
ISB | Instruction Synchronization Barrier (ISB), including CP15 encodings [1] | |
DMB | Data Memory Barrier (DMB), including CP15 encodings [1], if supported [2] | |
DSB | Data Synchronization Barrier (DSB), including CP15 encodings [1], if supported | |
ENTERX | Enter ThumbEE state | |
LEAVEX | Leave ThumbEE state | |
[1] Includes the CP15 encodings in ARMv7 and in earlier versions of the ARM architecture. [2] Bit [24] of the ETMCCER determines whether the PTM treats DMB and DSB operations as waypoint instructions, see Configuration Code Extension Register, ETMCCER. | ||
Table 2.4. Indirect branches, ARM instruction set
| Instruction | Description |
|---|---|
RFE | Return from Exception |
| Data processing instructions that modify the PC | |
BX | Branch and exchange |
BLX <reg> | Branch with link and exchange |
BXJ | Branch and exchange to Jazelle |
LDR or LDRT to the
PC | Load a word to the PC |
LDM including the PC | Load multiple to the PC |
Table 2.5. Indirect branches, Thumb and ThumbEE instruction sets
| Instruction | Description | |
|---|---|---|
| 16-bit instruction space | ||
ADD or MOV to the
PC | Data processing instruction that modifies the PC | |
BX | Branch and exchange | |
BLX <reg> | Branch with link and exchange | |
POP including the PC | Pop from the stack including the PC | |
HB, HBL, HBP,
or HBLP | Handler branches, ThumbEE instruction set only | |
| 32-bit instruction space | ||
RFE | Return from Exception | |
LDM including the PC | Load multiple to the PC | |
TBB or TBH | Table branch | |
BXJ | Branch and exchange to Jazelle | |
SUBS PC, LR | Data processing instruction that modifies the PC | |
LDR to the PC | Load a word to the PC | |
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