3.6. EmbeddedICE watchpoint comparator inputs

It is implementation defined whether a PTM implements any Embedded ICE watchpoint comparator inputs. If it does:

it implements between one and eight EmbeddedICE watchpoint comparator inputs
it might implement a single EmbeddedICE Watchpoint Behavior Control Register.

To find the number of EmbeddedICE comparator inputs implemented, read bits [19:16] of the Configuration Code Extension Register, see Configuration Code Extension Register, ETMCCER. If this field reads-as-zero then the implementation does not include any EmbeddedICE comparator inputs.

When a PTM implements one or more EmbeddedICE comparator inputs:

Each comparator input connects to a signal from the processor, that is asserted when the corresponding EmbeddedICE watchpoint is triggered. Typically, these are the RANGEOUT signals from the processor.
It is implementation defined whether the EmbeddedICE comparator inputs are inputs to the TraceEnable start/stop block. To check whether they are, read bit [20] of the Configuration Code Extension Register. This bit is 1 if the EmbeddedICE comparator inputs are inputs to the start/stop block.
Each Embedded ICE comparator input provides a PTM trace resource.
The PTM might implement the Embedded ICE Behavior Control Register, see EmbeddedICE Behavior Control Register, ETMEIBCR. To check whether this register is implemented, read bit [21] of the Configuration Code Extension Register. This bit is 1 if the EmbeddedICE Behavior Control Register is implemented. In this case, you can use this register to configure the behavior of each of the Embedded ICE comparator inputs.

The following sections give additional information about the behavior of the EmbeddedICE watchpoint comparator inputs:

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