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| Home > Program Trace Macrocell Programmer’s Model > Address comparators > Address range comparators (ARCs) | |||
The PTM has two modes of operation for ARCs:
In this mode, a match occurs when the instruction block overlaps the address range defined in the ARC. This means that the ARC matches if the processor executed an instruction in the range defined by the ARC. The PTM uses this mode for:
TraceEnable include control
the address range comparator events.
In include mode, the address comparator matches if:
(CompAddrLow ≤ END) AND (CompAddrHigh > START)
In this mode, a match occurs if the instruction block is completely within the address range defined in the ARC. This means that the ARC matches only if all of the instructions in the instruction block are in the exclude range defined by the ARC. The PTM uses this mode for:
TraceEnable exclude control.
In exclude mode, the address comparator matches if:
(CompAddrLow ≤ START) AND (CompAddrHigh > END)
See Terms used to describe address comparator behavior for descriptions of the terms used in this definition.
The ARC matches only if the address comparison is successful and the conditions defined in the corresponding Address Comparator Access Type Register are met.
The PTM holds the result of a successful ARC match until it processes another waypoint. The PTM event resource corresponding to the ARC is TRUE for this time.
On a processor reset, the ARCs maintain their values.
At each waypoint, the PTM always tests every pair of Address Comparator Value Registers as an ARC. For example, if it implements six Address Comparator Value Registers it always tests:
Address Comparator Value Registers 1 and 2 as ARC 1
Address Comparator Value Registers 3 and 4 as ARC 2
Address Comparator Value Registers 5 and 6 as ARC 3.
To avoid unexpected trace output, you must make sure you:
program the TraceEnable Control Register to select, for trace include or exclude, only the ARCs you have programmed
use only the ARC event resources that correspond to ARCs that you have programmed.
For a PTM that implements the maximum of 16 Address Comparator Value Registers, Table 3.3 lists the Address Comparator Value Registers that define each ARC.