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| Home > Program Trace Macrocell Programmer’s Model > Event resources and PTM events > Summary of the PTM events | |||
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| Home > Program Trace Macrocell Programmer’s Model > Event resources and PTM events > Summary of the PTM events | |||
Table 3.9 shows all of the registers that you can program to define PTM events. In some cases, it is implementation defined whether a register is implemented.
Table 3.9. The PTM event registers
| Event | Register | |
|---|---|---|
| Location | Description, see | |
| Trigger | 0x02 | Trigger Event Register, ETMTRIGGER |
| TraceEnable | 0x08 | TraceEnable Event Register, ETMTEEVR |
| Counter 1 enable | 0x54 | Counter Enable Event Registers, ETMCNTENR1 to ETMCNTENR4 |
| Counter 2 enable | 0x55 | |
| Counter 3 enable | 0x56 | |
| Counter 4 enable | 0x57 | |
| Counter 1 reload | 0x58 | Counter Reload Event Registers, ETMCNTRLDEVR1 to ETMCNTRLDEVR4 |
| Counter 2 reload | 0x59 | |
| Counter 3 reload | 0x5A | |
| Counter 4 reload | 0x5B | |
Sequencer transition, state 1 to state 2 |
| Sequencer State Transition Event Registers, ETMSQmnEVR |
Sequencer transition, state 2 to state 1 |
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Sequencer transition, state 2 to state 3 |
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Sequencer transition, state 3 to state 1 |
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Sequencer transition, state 3 to state 2 |
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Sequencer transition, state 1 to state 3 |
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| External output 1 event | 0x68 | External Output Event Registers, ETMEXTOUTEVR1 to ETMEXTOUTEVR4 |
| External output 2 event | 0x69 | |
| External output 3 event | 0x6A | |
| External output 4 event | 0x6B | |
| Timestamp event | 0x7E | Timestamp Event Register, ETMTSEVR |
| Copyright © 1999-2002, 2004-2008 ARM Limited. All rights reserved. | ARM IHI 0035A |
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