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CoreSight ™ Program Flow Trace ™ ArchitectureSpecification, v1.0

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CoreSight ™ Program Flow Trace ™ ArchitectureSpecification, v1.0

Copyright © 1999-2002, 2004-2008 ARM Limited. All rights reserved.

Proprietary notices

Table of Contents

About this specification

Product revision status
Intended audience
Using this specification
Conventions
Further reading

Feedback on the Program Flow Tracearchitecture
Feedback on this specification

1. Introduction

1.1. About the Program Trace Macrocell

1.1.1. Structure of a PTM
1.1.2. The debug environment
1.1.3. Thumb, ThumbEE, and Java support
1.1.4. Connections to a PTM
1.1.5. Trace compression
1.1.6. Resets

2. Program Flow Tracing

2.1. About Program Flow Tracing

2.1.1. Tracing branches
2.1.2. Tracing exceptions
2.1.3. Nonwaypoint instructions
2.1.4. PFT trace example

2.2. Waypoint instructions

2.2.1. Unpredictable encodings

2.3. Upgrading a nonwaypoint instructionon an exception

2.4. Timestamping

3. Program Trace Macrocell Programmer’s Model

3.1. About the PTM programmer’s model

3.2. CoreSight support

3.2.1. Programmer’s model requirements
3.2.2. Topology detection requirements

3.3. TraceEnable

3.3.1. About TraceEnable
3.3.2. TraceEnable rules
3.3.3. The TraceEnable start/stop block
3.3.4. TraceEnable Include/exclude control

3.4. Address comparators

3.4.1. General behavior of address comparators
3.4.2. Single address comparators (SACs)
3.4.3. Address range comparators (ARCs)

3.5. Context ID comparators

3.6. EmbeddedICE watchpoint comparatorinputs

3.6.1. EmbeddedICE watchpoint comparatorinput behavior
3.6.2. Default behavior of EmbeddedICE watchpointcomparator inputs
3.6.3. Pulse and latch behavior of EmbeddedICEwatchpoint comparator inputs
3.6.4. Examples of using EmbeddedICE watchpointcomparator inputs

3.7. Event resources and PTM events

3.7.1. The PTM event resources
3.7.2. Example PTM resourceconfiguration
3.7.3. Defining a PTM event
3.7.4. Summary of the PTM events

3.8. PTM counters

3.8.1. Use of PTM counters

3.9. The PTM sequencer

3.9.1. Use of the PTM sequencer

3.10. Instrumentation resources

3.10.1. The Instrumentationresource event resources
3.10.2. Instructions for controlling the Instrumentationresources
3.10.3. Instrumentation resource behavior when tracing parallelexecution

3.11. PTM input resources

3.11.1. External inputs
3.11.2. Extended external inputs
3.11.3. Non-secure state resource
3.11.4. Trace prohibited resource
3.11.5. Hard-wired TRUE resource

3.12. PTM external outputs

3.13. About the PTM registers

3.13.1. Register short names
3.13.2. PTM trace and PTM managementregisters
3.13.3. Accessing the PTM registers
3.13.4. Use of the Programmingbit
3.13.5. Synchronization of PTM register updates
3.13.6. Organization of the PTM registers

3.14. PTM register descriptions

3.14.1. Main Control Register, ETMCR
3.14.2. Configuration Code Register, ETMCCR
3.14.3. Trigger Event Register, ETMTRIGGER
3.14.4. Status Register, ETMSR
3.14.5. System ConfigurationRegister, ETMSCR
3.14.6. About the TraceEnablecontrol registers
3.14.7. TraceEnable Start/StopControl Register, ETMTSSCR
3.14.8. TraceEnable Event Register, ETMTEEVR
3.14.9. TraceEnable ControlRegister, ETMTECR1
3.14.10. FIFOFULL Level Register, ETMFFLR
3.14.11. About the address comparatorregisters
3.14.12. Address Comparator Value Registers, ETMACVR1 to ETMACVR16
3.14.13. Address ComparatorAccess Type Registers, ETMACTR1 to ETMACTR16
3.14.14. About the counterregisters
3.14.15. Counter Reload Value Registers, ETMCNTRLDVR1 to ETMCNTRLDVR4
3.14.16. Counter Enable EventRegisters, ETMCNTENR1 to ETMCNTENR4
3.14.17. Counter Reload EventRegisters, ETMCNTRLDEVR1 to ETMCNTRLDEVR4
3.14.18. Counter Value Registers, ETMCNTVR1 to ETMCNTVR4
3.14.19. About the sequencerregisters
3.14.20. Sequencer State TransitionEvent Registers, ETMSQmnEVR
3.14.21. Current Sequencer StateRegister, ETMSQR
3.14.22. External Output EventRegisters, ETMEXTOUTEVR1 to ETMEXTOUTEVR4
3.14.23. About the Context IDcomparator registers
3.14.24. Context ID ComparatorValue Registers, ETMCIDCVR1 to ETMCIDCVR3
3.14.25. Context ID ComparatorMask Register, ETMCIDCMR
3.14.26. Implementation specific registers, ETMIMPSPEC0 to ETMIMPSPEC7
3.14.27. Synchronization FrequencyRegister, ETMSYNCFR
3.14.28. ID Register, ETMIDR
3.14.29. Configuration CodeExtension Register, ETMCCER
3.14.30. Extended External InputSelection Register, ETMEXTINSELR
3.14.31. TraceEnable Start/StopEmbeddedICE Control Register, ETMTESSEICR
3.14.32. EmbeddedICE BehaviorControl Register, ETMEIBCR
3.14.33. Timestamp Event Register, ETMTSEVR
3.14.34. Auxiliary ControlRegister, ETMAUXCR
3.14.35. CoreSight Trace IDRegister, ETMTRACEIDR
3.14.36. About the OS Save andRestore registers
3.14.37. OS Lock Access Register, ETMOSLAR
3.14.38. OS Lock Status Register, ETMOSLSR
3.14.39. OS Save and Restore Register, ETMOSSRR
3.14.40. Device Power-Down StatusRegister, ETMPDSR
3.14.41. Integration Mode ControlRegister, ETMITCTRL
3.14.42. About the claim tag registers
3.14.43. Claim Tag Set Register, ETMCLAIMSET
3.14.44. Claim Tag Clear Register, ETMCLAIMCLR
3.14.45. About the lock registers
3.14.46. Lock Access Register, ETMLAR
3.14.47. Lock Status Register, ETMLSR
3.14.48. AuthenticationStatus Register, ETMAUTHSTATUS
3.14.49. Device ConfigurationRegister, ETMDEVID
3.14.50. Device Type Register, ETMDEVTYPE
3.14.51. About the peripheralidentification registers
3.14.52. Peripheral ID0 Register,ETMPIDR0
3.14.53. Peripheral ID1 Register,ETMPIDR1
3.14.54. Peripheral ID2 Register,ETMPIDR2
3.14.55. Peripheral ID3 Register,ETMPIDR3
3.14.56. Peripheral ID4 Register,ETMPIDR4
3.14.57. Peripheral ID5 to PeripheralID7 Registers, ETMPIDR5 to ETMPIDR7
3.14.58. About the componentidentification registers
3.14.59. Component ID0 Register,ETMCIDR0
3.14.60. Component ID1 Register,ETMCIDR1
3.14.61. Component ID2 Register,ETMCIDR2
3.14.62. Component ID3 Register,ETMCIDR3

3.15. Access controls for PTM registers

3.15.1. Access types
3.15.2. Meanings of terms and abbreviationsused in this section
3.15.3. Access permissions for memory-mappedaccesses
3.15.4. Access permissions for coprocessoraccesses

3.16. Power-down support

3.16.1. The process of saving and restoring the PTM state
3.16.2. PTM behavior when the OS Lock is set
3.16.3. Guidelines for the PTM trace registers to be savedand restored

3.17. Programming the PTM to trace all execution

4. Program Flow Trace Protocol

4.1. About the Program Flow Trace protocol

4.2. PFT atoms

4.3. Summary of PFT packets

4.4. Cycle-accurate tracing

4.5. PFT packet formats

4.5.1. A-sync, alignment synchronizationpacket
4.5.2. I-sync, instruction synchronizationpacket
4.5.3. Atom packet
4.5.4. Branch address packet
4.5.5. Waypoint update packet
4.5.6. Trigger packet
4.5.7. Context ID packet
4.5.8. Timestamp packet
4.5.9. Exception return packet
4.5.10. Ignore packet

4.6. Branch broadcasting

4.7. Prohibited regions

4.7.1. Behavior of the PTMwhen the processor is in a prohibited region

4.8. Trace FIFO overflow

4.9. Wait for Interrupt and Wait for Event

4.10. Large blocks of instructions

4.11. Synchronization

4.11.1. Periodic synchronization
4.11.2. Alignment synchronization
4.11.3. Instruction synchronization
4.11.4. Timestamp synchronization

4.12. Tracing security state changes

4.12.1. Changing from Non-secure to Securestate
4.12.2. Changing from Secure to Non-securestate

4.13. Use of a return stack

4.14. Timestamping

4.15. Trace flushing

4.15.1. CoreSight or other ATB flush request
4.15.2. Setting the Programming bit or theOS Lock
4.15.3. WFI or WFE request
4.15.4. Non-invasive debugdisabled

4.16. Tracing Thumb instructions

4.16.1. 32-bit Thumb instructions
4.16.2. Thumb CBZ and CBNZ instructions

4.17. Jazelle state

4.18. Debug state

5. Tracing Exceptions

5.1. About exception tracing in the PFTarchitecture

5.2. The different exception cases

5.2.1. Exception occurs after a nonwaypointinstruction
5.2.2. Exception occurs immediately aftera waypoint instruction
5.2.3. Exception occurs immediately afteranother exception
5.2.4. Exception occurs immediately aftertrace turn-on

5.3. Tracing the different exception types

5.3.1. Processor reset exception
5.3.2. Undefined Instruction exception
5.3.3. SVC (Supervisor Call) or SMC (SecureMonitor Call) exception
5.3.4. Prefetch Abort exception
5.3.5. Synchronous Data Abort exception
5.3.6. Asynchronous Data Abort,FIQ or IRQ exception
5.3.7. Debug state entry, when Halting debug-modeis enabled
5.3.8. ThumbEE check that goes to a handler,including the CHKA instruction
5.3.9. Jazelle exception that goes to anARM or Thumb state handler
5.3.10. Secure to Non-secure state change
5.3.11. Other exceptions

5.4. Waypoint update addresses

A. PTM Quick Reference Information

A.1. PTM event resources

A.1.1. Resource identification and eventencoding
A.1.2. Resource control registers

A.2. Summary of implementationdefined PTM features

B. Trace Decompressor Operation

B.1. About PTM trace decompression

B.2. PFT trace state and objects

B.2.1. PFT state information
B.2.2. PFT output objects

B.3. PFT trace decompression flow

B.3.1. Overall PFT trace decompression flow
B.3.2. Details of PFT trace decompressionoperations

C. Software Issues for PFT

C.1. About tracing dynamically-loaded code

C.1.1. Simple overlay support

C.2. Software support for Context ID

C.3. Hardware support for Context ID

List of Figures

1.1. Example debugging environment
1.2. Main connections to a PTM
3.1. The TraceEnable mechanism
3.2. Programming the TraceEnable logic
3.3. Example resource configuration
3.4. Defining a PTM event
3.5. Sequencer state diagram
3.6. Extended external inputs implementationexample
3.7. Mapping from register number to CP14 MRC or MCR instructionfields
3.8. Programming PTM registers
3.9. Main Control Register bit assignments
3.10. Configuration Code Register bit assignments
3.11. Trigger Event Register bit assignments
3.12. Status Register bit assignments
3.13. System Configuration Register bitassignments
3.14. TraceEnable Start/Stop Control Registerbit assignments
3.15. TraceEnable Event Register bit assignments
3.16. TraceEnable Control Register bitassignments
3.17. FIFOFULL Level Register bit assignments
3.18. Address Comparator Value Registers,bit assignments
3.19. Address Comparator Access Type Registers,bit assignments
3.20. Counter Reload Value Registers, bitassignments
3.21. Counter Enable Event Registers, bitassignments
3.22. Counter Reload Event Registers, bitassignments
3.23. Counter Value Registers, bit assignments
3.24. Sequencer State Transition EventRegisters, bit assignments
3.25. Current Sequencer State Registerbit assignments
3.26. External Output Event Registers,bit assignments
3.27. Context ID Comparator Value Registers,bit assignments
3.28. Context ID Comparator Mask Registerbit assignments
3.29. Implementationspecific Register 0 bit assignments
3.30. Synchronization Frequency Registerbit assignments
3.31. ID Register bit assignments, foran ARM implementation
3.32. Configuration Code Extension Registerbit assignments
3.33. Extended External Input SelectionRegister bit assignments
3.34. TraceEnable Start/Stop EmbeddedICEControl Register bit assignments
3.35. EmbeddedICE Behavior Control Registerbit assignments
3.36. Timestamp Event Register bit assignments
3.37. CoreSight Trace ID Register bit assignments
3.38. OS Lock Access Register bit assignments
3.39. OS Lock Status Register bit assignments
3.40. OS Save and Restore Register bitassignments
3.41. Power-Down Status Register bit assignments
3.42. Integration Mode Control Registerbit assignments
3.43. Claim Tag Set Register bit assignments
3.44. Claim Tag Clear Register bit assignments
3.45. Lock Access Register bit assignments
3.46. Lock Status Register bit assignments
3.47. Authentication Status Register bitassignments
3.48. Secure non-invasive debug enablelogic when controlled by the PTM
3.49. Device Configuration Register bitassignments
3.50. Device Type Register bit assignments
3.51. Mapping between the Peripheral IDRegisters and the Peripheral ID value
3.52. Peripheral ID fields for an ARM implementation
3.53. Peripheral ID0 Register bit assignments
3.54. Peripheral ID1 Register bit assignments
3.55. Peripheral ID2 Register bit assignments
3.56. Peripheral ID3 Register bit assignments
3.57. Peripheral ID4 Register bit assignments
3.58. Peripheral ID5 to Peripheral ID7Registers, bit assignments
3.59. Mapping between the Component IDRegisters and theComponent ID value
3.60. Component ID0 Register bit assignments
3.61. Component ID1 Register bit assignments
3.62. Component ID2 Register bit assignments
3.63. Component ID3 Register bit assignments
4.1. A-sync alignment synchronizationpacket
4.2. I-sync instruction synchronizationpacket
4.3. Atom packet, cycle-accurate tracingnot enabled
4.4. Cycle-accurate atom packet
4.5. Full branch address packet with exception,ARM state
4.6. Full branch address packet with exception,Thumb state
4.7. Full branch address packet with exception,Jazelle state
4.8. Branch address packet cycle countbytes, when cycle-accurate tracing is enabled
4.9. Address bytes when bit [11] is themost significant bit that changes, in Thumb state
4.10. Branch to Thumb state with changein A[6:1], no exception information byte
4.11. Branch to Thumb state with changein A[12:7], no exception information byte
4.12. Branch to Thumb state with changein A[19:13], no exception information byte
4.13. Branch to Thumb state with changein A[26:20], no exception information byte
4.14. Branch to Thumb state with changein A[31:27], no exception information byte
4.15. Branch to Thumb state with change in A[12:1], withexception information byte
4.16. Branch to Thumb state with changein A[12:1], with two exception information bytes
4.17. Branch to Thumb state with change in A[19:13], withexception information byte
4.18. Branch to Thumb state with change in A[26:20], withexception information byte
4.19. Branch to Thumb state with changein A[31:27], with exception information byte
4.20. Branch to ARM state with change in A[7:2], no exceptioninformation byte
4.21. Branch to ARM state with change in A[13:8], no exceptioninformation byte
4.22. Branch to ARM state with change in A[20:14], no exceptioninformation byte
4.23. Branch to ARM state with change in A[27:21], no exceptioninformation byte
4.24. Branch to ARM state with change inA[31:28], no exception information byte
4.25. Branch to ARM state with change in A[13:2], withexception information byte
4.26. Branch to ARM state with change in A[20:14], withexception information byte
4.27. Branch to ARM state with change in A[27:21], withexception information byte
4.28. Branch to ARM state with change in A[31:28], withexception information byte
4.29. Cycle count bytes when bit [13] isthe MS nonzero bit
4.30. Cycle count byte when MS nonzerobit is in Count[3:0]
4.31. Cycle count bytes when MS nonzerobit is in Count[10:4]
4.32. Cycle count bytes when MS nonzerobit is in Count[17:11]
4.33. Cycle count bytes when MS nonzerobit is in Count[24:18]
4.34. Cycle count bytes when MS nonzerobit is in Count[31:25]
4.35. Waypoint update packet, ARM state
4.36. Waypoint update packet, Thumb state
4.37. Trigger packet
4.38. Context ID packet
4.39. Timestamp packet
4.40. Exception return packet, ARMv7-Mtrace only
4.41. Ignore packet
A.1. Writing to an Event Register
B.1. Trace decompression operation
C.1. SRAM overlay examples
C.2. Memory map and overlay physical addressspace

List of Tables

2.1. PTM trace example
2.2. Direct branches, ARM instruction set
2.3. Direct branches, Thumb and ThumbEE instruction sets
2.4. Indirect branches, ARM instruction set
2.5. Indirect branches, Thumb and ThumbEE instruction sets
3.1. Required PTM logical interfaces
3.2. Permitted instruction block end addresses
3.3. Definition of ARCs by Address Comparator Value Registers
3.4. Default behavior of EmbeddedICE watchpoint comparator inputs
3.5. Event resource definitions
3.6. Additional information about the PTM event resources
3.7. Boolean operations for defining PTM events
3.8. Defining a PTM event
3.9. The PTM event registers
3.10. The Instrumentation resource event resources
3.11. Hint field encodings for the Instrumentation instructions
3.12. Instrumentation resource parallel execution examples, fortwo instructions
3.13. Examples of register short names
3.14. Split of PTM register map into trace and management registers
3.15. Typical PTM register access implementations
3.16. PTM registers summary
3.17. Main Control Register bit assignments
3.18. Configuration Code Register bit assignments
3.19. Trigger Event Register bit assignments
3.20. Status Register bit assignments
3.21. System Configuration Register bit assignments
3.22. TraceEnable Start/Stop Control Register bit assignments
3.23. TraceEnable Event Register bit assignments
3.24. TraceEnable Control Register bit assignments
3.25. FIFOFULL Level Register bit assignments
3.26. Address Comparator Value Registers, bit assignments
3.27. Address Comparator Access Type Registers, bit assignments
3.28. Summary of Counter registers
3.29. Counter Reload Value Registers, bit assignments
3.30. Counter Enable Event Registers, bit assignments
3.31. Counter Reload Event Registers, bit assignments
3.32. Counter Value Registers, bit assignments
3.33. Sequencer register allocation
3.34. Sequencer State Transition Event Registers, bit assignments
3.35. Current Sequencer State Register bit assignments
3.36. External Output Event Registers, bit assignments
3.37. Summary of the Context ID comparator registers
3.38. Context ID Comparator Value Registers, bit assignments
3.39. Context ID Comparator Mask Register bit assignments
3.40. Implementation specific Register0 bit assignments
3.41. Synchronization Frequency Register bit assignments
3.42. ID Register bit assignments
3.43. Configuration Code Extension Register bit assignments
3.44. Extended External Input Selection Register bit assignments
3.45. TraceEnable Start/Stop EmbeddedICE Control Register bit assignments
3.46. EmbeddedICE Behavior Control Register bit assignments
3.47. Timestamp Event Register bit assignments
3.48. CoreSight Trace ID Register bit assignments
3.49. OS Lock Access Register bit assignments
3.50. OS Lock Status Register bit assignments
3.51. OS Save and Restore Register bit assignments
3.52. Power-Down Status Register bit assignments
3.53. ETMPDSR encodings
3.54. Integration Mode Control Register bit assignments
3.55. Claim Tag Set Register bit assignments
3.56. Claim Tag Clear Register bit assignments
3.57. Lock Access Register bit assignments
3.58. Lock Status Register bit assignments
3.59. Authentication Status Register bit assignments
3.60. Implementation of the Secure non-invasive debug field
3.61. Device Configuration Register bit assignments
3.62. Device Type Register bit assignments
3.63. Summary of the peripheral identification registers
3.64. Register fields for the Peripheral ID registers
3.65. Peripheral ID0 Register bit assignments
3.66. Peripheral ID1 Register bit assignments
3.67. Peripheral ID2 Register bit assignments
3.68. Peripheral ID3 Register bit assignments
3.69. Peripheral ID4 Register bit assignments
3.70. Peripheral ID5 to Peripheral ID7 Registers, bit assignments
3.71. Summary of the component identification registers
3.72. Component ID0 Register bit assignments
3.73. Component ID1 Register bit assignments
3.74. Component ID2 Register bit assignments
3.75. Component ID3 Register bit assignments
3.76. Debugger accesses to PTM memory-mapped registers, excepttheOS Save and Restore registers, separate debug and core power domains
3.77. Debugger accesses to PTM memory-mapped OS Save and Restoreregisters, separate debug and core power domains
3.78. Software accesses to PTM memory-mapped registers, exceptthe OSSave and Restore registers, separate debug and core power domains
3.79. Software accesses to PTM memory-mapped OS Save and Restoreregisters, separate debug and core power domains
3.80. Debugger accesses to PTM memory-mapped registers, excepttheOS Save and Restore registers, for SinglePower system
3.81. Debugger accesses to PTM memory-mapped OS Save and Restoreregisters, for SinglePower system
3.82. Software accesses to PTM memory-mapped registers, excepttheOS Save and Restore registers, for SinglePower system
3.83. Software accesses to PTM memory-mapped OS Save and Restoreregisters, for SinglePower system
3.84. Coprocessor accesses to PTM registers, separate debug andcore power domains
3.85. Coprocessor accesses to PTM registers, for SinglePower system
3.86. Typical list of PTM registers to be saved and restored
4.1. Packet formats
4.2. Cycle count example with late trace turn-on
4.3. Atom header encoding when cycle-accurate tracing is not enabled
4.4. Values of Exception[3:0] for ARMv7-A and ARMv7-R processors
4.5. Number of address bytes generated for branch address packets
4.6. Interpretation of bit [7] in address byte 0
4.7. Interpretation of bits [7:6] in the address bytes 1-4
4.8. Number cycle count bytes generated for branch address packets
4.9. Permitted waypoint address outputs in waypoint update packets
4.10. Tracing a change of Context ID
4.11. Branch with link instructions
4.12. PTM branch tracing when using the return stack
5.1. Tracing an exception occurring after execution of a nonwaypointinstruction
5.2. Tracing an exception immediately after execution of a waypointinstruction
5.3. Tracing back-to-back exceptions
5.4. Normal tracing of an FIQ after executing a branch at theIRQ vector address
5.5. Normal tracing of an FIQ after executing a NOP atthe IRQ vector address
5.6. Descriptions of how a PTM traces different exceptions
5.7. Tracing a synchronous Data Abort exception after a waypointinstruction
5.8. Tracing a synchronous Data Abort exception after a nonwaypointinstruction
5.9. Waypoint update instruction addresses for exceptions in ARMstate
5.10. Waypoint update instruction addresses for exceptions in Thumbstate
A.1. Resource identification encoding
A.2. Boolean function encoding for events
A.3. Locations of PTM event registers
A.4. Trace Start/Stop Resource Control Register, 0x006
A.5. TraceEnable Control Register, 0x009
A.6. FIFOFULL Level Register, 0x00B
A.7. Address Comparator Value Registers, 0x010 -0x01F
A.8. Address Comparator Access Type Registers, 0x020 -0x02F
A.9. Counter Reload Value Registers, 0x050 -0x053
A.10. Counter Value Registers, 0x05C -0x05F
A.11. Current Sequencer State Register, 0x067
A.12. Locations of the Context ID Comparator Value Registers
A.13. Context ID Comparator Value Registers, 0x06C -0x06E
A.14. Context ID Comparator Mask Register, 0x06F
A.15. Synchronization Frequency Register, 0x078
A.16. Extended External Input Selection Register, 0x07B
A.17. PTM features with implementationdefined number of instances or size
A.18. Optional features in a PTM

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The product described in this document is subject to continuousdevelopments and improvements. All particulars of the product andits use contained in this document are given by ARM in good faith.However, all warranties implied or expressed, including but notlimited to implied warranties of merchantability, or fitness forpurpose, are excluded.

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Where the term ARM is used it means “ARM or any of its subsidiariesas appropriate”.

ConfidentialityStatus

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Product Status

The information in this document is final, that is for a developedproduct.

Revision History
Revision A	09April 2008	First release for v1.0

Copyright © 1999-2002, 2004-2008 ARM Limited. All rights reserved.	ARM IHI 0035A
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