2.2. Waypoint instructions

The following tables list the ARMv7 instructions that are always classified as waypoint instructions:

Unpredictable encodings describes the PFT requirements when the processor attempts to execute an instruction encoding that the architecture defines as unpredictable.

Table 2.2. Direct branches, ARM instruction set

InstructionDescription
BUnconditional branch
B<cc>Conditional Branch
BLBranch and Link
BLX <immed>Branch with link and exchange
ISBInstruction Synchronization Barrier (ISB), including CP15 encodings [a]
DMBData Memory Barrier (DMB), including CP15 encodings [a], if supported[b]
DSBData Synchronization Barrier (DSB), including CP15 encodings [a], if supported [b]

[a] Includes the CP15 encodings in ARMv7 and in earlier versions of the ARM architecture.

[b] Bit [24] of the ETMCCER determines whether the PTM treats DMB and DSB operations as waypoint instructions, see Configuration Code Extension Register, ETMCCER.


Table 2.3. Direct branches, Thumb and ThumbEE instruction sets

InstructionDescription
16-bit instruction space
 BUnconditional branch
B<cc>Conditional Branch
CZB or CNZBCompare with zero and branch
32-bit instruction space
 BUnconditional branch
B<cc>Conditional Branch
BL <immed>Branch and Link
BLX <immed>Branch with link and exchange
ISBInstruction Synchronization Barrier (ISB), including CP15 encodings [a]
DMBData Memory Barrier (DMB), including CP15 encodings [a], if supported [b]
DSBData Synchronization Barrier (DSB), including CP15 encodings [a], if supported
ENTERXEnter ThumbEE state
LEAVEXLeave ThumbEE state

[a] Includes the CP15 encodings in ARMv7 and in earlier versions of the ARM architecture.

[b] Bit [24] of the ETMCCER determines whether the PTM treats DMB and DSB operations as waypoint instructions, see Configuration Code Extension Register, ETMCCER.


Table 2.4. Indirect branches, ARM instruction set

InstructionDescription
RFEReturn from Exception
Data processing instructions that modify the PC
BXBranch and exchange
BLX <reg>Branch with link and exchange
BXJBranch and exchange to Jazelle
LDR or LDRT to the PCLoad a word to the PC
LDM including the PCLoad multiple to the PC
ERETException return, when Virtualization is supported

Table 2.5. Indirect branches, Thumb and ThumbEE instruction sets

InstructionDescription
16-bit instruction space
 ADD or MOV to the PCData processing instruction that modifies the PC
BXBranch and exchange
BLX <reg>Branch with link and exchange
POP including the PCPop from the stack including the PC
HB, HBL, HBP, or HBLPHandler branches, ThumbEE instruction set only
32-bit instruction space
 RFEReturn from Exception
LDM including the PCLoad multiple to the PC
TBB or TBHTable branch
BXJBranch and exchange to Jazelle
SUBS PC, LRData processing instruction that modifies the PC
LDR to the PCLoad a word to the PC
ERETException return, when Virtualization is supported

Note

There are waypoint instructions which are permitted in other modes but are undefined in Hyp mode. When in Hyp mode, the following instructions are not waypoints:

  • RFE

  • SUBS PC, LR, #N, where N is not zero, when executing in Thumb state

  • all flag setting data processing operations with the PC as the target register, when executing in ARM state

  • LDM (exception return).

Where these instructions might also have been classified as exception return instructions, they are not classified as exception return instructions when in Hyp mode.

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