3.16.42. Device Power-Down Status Register, ETMPDSR

The ETMPDSR characteristics are:

Purpose

This register indicates the power-down status of the PTM.

Usage constraints

There are no usage constraints.

Configurations

Available in all PTM implementations.

Attributes

See the register summary in Table 3.16.

Figure 3.47 shows the ETMPDSR bit assignments.

Figure 3.47. ETMPDSR bit assignments

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Table 3.57 shows the ETMPDSR bit assignments.

Table 3.57. ETMPDSR bit assignments

BitsDescription
[31:6]

Reserved, RAZ.

[5]For PFTv1.0 this bit is Reserved, RAZ.

LK bit.

From PFTv1.1 this bit indicates the status of the OS Lock. The possible values of this bit are:

0

PTM trace registers are not locked.

1

PTM trace registers are locked. Any access to these registers returns a slave-generated error response. See Power-down support for more information

If the OS Lock is implemented, this field is set from a PTM reset. The external debugger must always clear the OS Lock after system power on reset, before it can access trace registers.

[4:2]Reserved, RAZ.
[1]

Sticky Register state bit. The possible values of this bit are:

0

PTM trace registers have not been powered down since this register was last read.

1

PTM trace registers have been powered down since this register was last read, and have lost their state.

This bit is cleared to 0 on reading this register if the core power domain of the PTM is currently powered up, indicated by bit [0] being set to 1.

When the core power domain of the PTM is powered down, this bit is set to 1.

Reads of this register when the core power domain is powered down return 1 for this bit, and do not change the value of this bit.

Reads of this register when the core power domain is powered up return the current value of this bit, and then clear this bit to 0. If the Software Lock mechanism is locked and the ETMPDSR read is made through the memory mapped interface, this bit is not cleared.

When this bit is set to 1, an access to any PTM Trace Register returns an error response.

[0]

PTM powered up bit.

The value of this bit indicates whether you can access the PTM trace registers. The possible values are:

0

PTM trace registers cannot be accessed.

1

PTM trace registers can be accessed.

Usually, an external input to the PTM, driven by the system power controller, controls the value of this bit.

When this bit is set to 0, an access to any PTM trace register returns an error response.


Table 3.58 shows the different encodings of the ETMPDSR.

Table 3.58. ETMPDSR encodings

Bit [1]

Sticky Register state

Bit [0]

PTM powered up

Meaning
00PTM trace registers are inaccessible. No state has been lost.
01PTM trace registers are accessible.
10PTM trace registers are powered down, inaccessible, and their state has been lost.
11PTM trace registers are powered up. However, their state has been lost because of a power down.

This register must be implemented in:

If the PTM only occupies a single power domain, this register might always read as 0x00000001, indicating that the PTM is powered up and accessible. In this case, if the PTM is not powered up:

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