3.16.26. Implementation specific registers, ETMIMPSPEC0 to ETMIMPSPEC7

Register numbers 0x70-0x77 in the register map are reserved for up to eight implementation specific registers. Even when a PTM does not implement these registers, implementation specific Register 0, register number 0x70, must be partially defined, so that a debugger can implement a general mechanism for detecting implementation specific extensions.

See Table 3.16 for details of access to this register area.

Implementation specific Register 0

The implementation specific Register 0 characteristics are:

Purpose

Shows the presence of any implementation specific features, and enables any features that are provided.

Usage constraints

There are no usage constraints.

Configurations

Available in all PTM implementations.

Attributes

See the register summary in Table 3.16.

Figure 3.33 shows the implementation specific Register 0 default bit assignments.

Figure 3.33. Implementation specific Register 0 bit assignments

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Table 3.42 shows the implementation specific Register 0 default bit assignments.

Table 3.42. Implementation specific Register 0 bit assignments

Bits

Access

Description

[31:8]

-Reserved
[7:4]RW

Enable implementation specific extensions. When these bits are b0000 the PTM must behave as if the implementation specific extensions are not implemented. The behavior of the PTM is implementation defined when these bits are set to any value other than b0000.

A PTM reset sets these bits to b0000.

[3:0]ROIf this field is b0000 then the PTM does not support any implementation specific extensions. Other values are for use only as permitted in writing by ARM Limited.

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